Patents by Inventor Kazunori Miyoshi

Kazunori Miyoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11915951
    Abstract: A plasma processing apparatus includes a stage disposed in a processing chamber for mounting a wafer, a plasma generation chamber disposed above the processing chamber for plasma generation using process gas, a plate member having multiple introduction holes, made of a dielectric material, disposed above the stage and between the processing chamber and the plasma generation chamber, and a lamp disposed around the plate member for heating the wafer. The plasma processing apparatus further includes an external IR light source, an emission fiber arranged in the stage, that outputs IR light from the external IR light source toward a wafer bottom, and a light collection fiber for collecting IR light from the wafer. Data obtained using only IR light from the lamp is subtracted from data obtained also using IR light from the external IR light source during heating of the wafer. Thus, a wafer temperature is determined.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: February 27, 2024
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Hiroyuki Kobayashi, Nobuya Miyoshi, Kazunori Shinoda, Tatehito Usui, Naoyuki Kofuji, Yutaka Kouzuma, Tomoyuki Watanabe, Kenetsu Yokogawa, Satoshi Sakai, Masaru Izawa
  • Publication number: 20220300833
    Abstract: A feature extraction device 80 includes a feature extraction unit 81 which extracts a feature indicated by time-series data by machine learning using a recurrence plot generated from the time-series data.
    Type: Application
    Filed: September 6, 2019
    Publication date: September 22, 2022
    Applicant: NEC Corporation
    Inventor: Kazunori MIYOSHI
  • Patent number: 11032144
    Abstract: A network control system includes link design unit for deciding, as a configuration of one network formed by connecting a plurality of nodes having a communication function, a configuration of distributed networks included in the network and specific links for forming the network by connecting the distributed networks; and network configuration switching unit for switching the configuration of the network by logically enabling or disabling the specific links on request at least in a state where links other than the specific links are enabled, in which the link design unit decides the configuration of the distributed networks and the specific links based on a cluster hierarchical structure corresponding to a formation process of the one network which is formed as a result of sequentially adding links, which connect the nodes, based on a connection weight decided in accordance with a degree of spread or complexity of the network after connection.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: June 8, 2021
    Assignee: NEC CORPORATION
    Inventor: Kazunori Miyoshi
  • Publication number: 20200195502
    Abstract: A network control system includes link design unit for deciding, as a configuration of one network formed by connecting a plurality of nodes having a communication function, a configuration of distributed networks included in the network and specific links for forming the network by connecting the distributed networks; and network configuration switching unit for switching the configuration of the network by logically enabling or disabling the specific links on request at least in a state where links other than the specific links are enabled, in which the link design unit decides the configuration of the distributed networks and the specific links based on a cluster hierarchical structure corresponding to a formation process of the one network which is formed as a result of sequentially adding links, which connect the nodes, based on a connection weight decided in accordance with a degree of spread or complexity of the network after connection.
    Type: Application
    Filed: July 12, 2017
    Publication date: June 18, 2020
    Applicant: NEC CORPORATION
    Inventor: Kazunori MIYOSHI
  • Patent number: 9742665
    Abstract: A communication network control system (1) eliminates, in a communication network (G) in which a plurality of nodes (Ni) are connected via a plurality of links (2), a node (Nx) having a trouble and implements a reconnection in the communication network (G).
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: August 22, 2017
    Assignee: NEC Corporation
    Inventor: Kazunori Miyoshi
  • Publication number: 20150334007
    Abstract: A communication network control system (1) eliminates, in a communication network (G) in which a plurality of nodes (Ni) are connected via a plurality of links (2), a node (Nx) having a trouble and implements a reconnection in the communication network (G).
    Type: Application
    Filed: August 13, 2013
    Publication date: November 19, 2015
    Applicant: NEC Corporation
    Inventor: Kazunori MIYOSHI
  • Patent number: 8493882
    Abstract: Provided is an optimization evaluation system, wherein the effect of the optimization of traffic characteristic in a communication network is quantitatively evaluated. An optimization evaluation system which evaluates effects of optimization done by an optimization function in a communication network that has the optimization function for optimizing a communication traffic characteristic, including: a communication traffic analyzing module which acquires a communication traffic variation distribution based on measured communication traffic data; and a communication traffic evaluation module which executes processing for quantitatively evaluating the effects of the optimization of the communication traffic characteristic executed by the optimization function based on a fact whether or not the variation distribution calculated by the communication traffic analyzing module is a power function.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: July 23, 2013
    Assignee: NEC Corporation
    Inventor: Kazunori Miyoshi
  • Publication number: 20110058498
    Abstract: Provided is an optimization evaluation system, wherein the effect of the optimization of traffic characteristic in a communication network is quantitatively evaluated. An optimization evaluation system which evaluates effects of optimization done by an optimization function in a communication network that has the optimization function for optimizing a communication traffic characteristic, including: a communication traffic analyzing module which acquires a communication traffic variation distribution based on measured communication traffic data; and a communication traffic evaluation module which executes processing for quantitatively evaluating the effects of the optimization of the communication traffic characteristic executed by the optimization function based on a fact whether or not the variation distribution calculated by the communication traffic analyzing module is a power function.
    Type: Application
    Filed: April 9, 2009
    Publication date: March 10, 2011
    Inventor: Kazunori Miyoshi
  • Patent number: 7783143
    Abstract: A semiconductor device has printed wiring board (11) where electric wiring (18) connected to LSI chip (17) and to planar optical element (21) is formed, and where optical waveguide (25) which transfers light inputted into planar optical element (21) and/or light outputted from planar optical element (21) is fixed. Planar optical element (21) is mounted in one end of small substrate (13), and another end of small substrate (13) is connected to printed wiring board (11) by solder bump (26). One end of small substrate (13) where planar optical element (21) is mounted is fixed to printed wiring board (11) by a fixing mechanism. Small substrate (13) has flexible section (15), which is easily deformable compared with other portions of printed wiring board (11) and small substrate (13), in at least a partial region between one end where planar optical element (21) is mounted and another end electrically connected to printed wiring board (11).
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: August 24, 2010
    Assignee: NEC Corporation
    Inventors: Kazunori Miyoshi, Kazuhiko Kurata, Takanori Shimizu, Ichiro Hatakeyama, Junichi Sasaki
  • Publication number: 20090269078
    Abstract: A dispersion compensator (1) has a substrate (2) made of a resin, on which a conductor layer (3a), a dielectric layer (4a), a wiring layer (5a), a dielectric layer (4b), a wiring layer (5b), a dielectric layer (4c), and a conductor layer (3b) are provided in this order. A transmission line (6a) forming the wiring layer (5a) and a transmission line (6b) forming the wiring layer (5b) have identical shapes to each other and have equivalent dispersion characteristics to each other. The transmission lines (6a) and (6b) are formed in a meander shape and are arranged to overlap with each other as viewed in plan. Differential signals (14) and (15) are input to the transmission lines (6a) and (6b), respectively.
    Type: Application
    Filed: February 16, 2006
    Publication date: October 29, 2009
    Inventor: Kazunori Miyoshi
  • Patent number: 7561762
    Abstract: A semiconductor device has printed wiring board (11) where electric wiring (18) connected to LSI chip (17) and to planar optical element (21) is formed, and where optical waveguide (25) which transfers light inputted into planar optical element (21) and/or light outputted from planar optical element (21) is fixed. Planar optical element (21) is mounted in one end of small substrate (13), and another end of small substrate (13) is connected to printed wiring board (11) by solder bump (26). One end of small substrate (13) where planar optical element (21) is mounted is fixed to printed wiring board (11) by a fixing mechanism. Small substrate (13) has flexible section (15), which is easily deformable compared with other portions of printed wiring board (11) and small substrate (13), in at least a partial region between one end where planar optical element (21) is mounted and another end electrically connected to printed wiring board (11).
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: July 14, 2009
    Assignee: NEC Corporation
    Inventors: Kazunori Miyoshi, Kazuhiko Kurata, Takanori Shimizu, Ichiro Hatakeyama, Junichi Sasaki
  • Patent number: 7473038
    Abstract: An optical connector according to the present invention including a connector body mounted on an optical module mounted on a circuit board, and a connector fixing member for pressing the connector body against the optical module. The connector fixing member can be engaged/disengaged with/from the circuit board, and thus the connector body can be attached/detached to/from the optical module.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: January 6, 2009
    Assignees: Fujikura Ltd., NEC Corporation
    Inventors: Kunihiko Fujiwara, Akito Nishimura, Kenji Sasaki, Yukio Hayashi, Ichiro Hatakeyama, Youichi Hashimoto, Junichi Sasaki, Ryosuke Kuribayashi, Kazunori Miyoshi, Kazuhiko Kurata
  • Patent number: 7333683
    Abstract: An LSI package having an optical interface is mounted on a surface of a photoelectric wiring board. The photoelectric wiring board and the optical interface are optically connected with sufficient precision. A wiring board side guide member including socket pins and guide pins is soldered and fixed onto the photoelectric wiring board including an optical transmission line, a guide pin, and a mirror. An optical interface side guide member having a fitting hole is glued to the optical interface. The optical interface is mounted on an interposer of the LSI package. The guide pin of the photoelectric wiring board is fitted into the fitting hole formed through the interposer. The guide pin of the guide member is fitted into the fitting hole of the guide member. As a result, position alignment between the optical interface and the photoelectric wiring board is conducted with high precision.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: February 19, 2008
    Assignee: NEC Corproation
    Inventors: Junichi Sasaki, Ichiro Hatakeyama, Kazunori Miyoshi, Hikaru Kouta, Kaichiro Nakano, Mikio Oda, Hisaya Takahashi, Mitsuru Kurihara
  • Publication number: 20080036021
    Abstract: A semiconductor device has printed wiring board (11) where electric wiring (18) connected to LSI chip (17) and to planar optical element (21) is formed, and where optical waveguide (25) which transfers light inputted into planar optical element (21) and/or light outputted from planar optical element (21) is fixed. Planar optical element (21) is mounted in one end of small substrate (13), and another end of small substrate (13) is connected to printed wiring board (11) by solder bump (26). One end of small substrate (13) where planar optical element (21) is mounted is fixed to printed wiring board (11) by a fixing mechanism. Small substrate (13) has flexible section (15), which is easily deformable compared with other portions of printed wiring board (11) and small substrate (13), in at least a partial region between one end where planar optical element (21) is mounted and another end electrically connected to printed wiring board (11).
    Type: Application
    Filed: September 20, 2005
    Publication date: February 14, 2008
    Applicant: NEC CORPORATION
    Inventors: Kazunori Miyoshi, Kazuhiko Kurata, Takanori Shimizu, Ichiro Hatakeyama, Junichi Sasaki
  • Publication number: 20060280410
    Abstract: An optical connector according to the present invention including a connector body mounted on an optical module mounted on a circuit board, and a connector fixing member for pressing the connector body against the optical module. The connector fixing member can be engaged/disengaged with/from the circuit board, and thus the connector body can be attached/detached to/from the optical module.
    Type: Application
    Filed: May 22, 2006
    Publication date: December 14, 2006
    Inventors: Kunihiko Fujiwara, Akito Nishimura, Kenji Sasaki, Yukio Hayashi, Ichiro Hatakeyama, Youichi Hashimoto, Junichi Sasaki, Ryosuke Kuribayashi, Kazunori Miyoshi, Kazuhiko Kurata
  • Publication number: 20060078248
    Abstract: An LSI package having an optical interface is mounted on a surface of a photoelectric wiring board. The photoelectric wiring board and the optical interface are optically connected with sufficient precision. A wiring board side guide member including socket pins and guide pins is soldered and fixed onto the photoelectric wiring board including an optical transmission line, a guide pin, and a mirror. An optical interface side guide member having a fitting hole is glued to the optical interface. The optical interface is mounted on an interposer of the LSI package. The guide pin of the photoelectric wiring board is fitted into the fitting hole formed through the interposer. The guide pin of the guide member is fitted into the fitting hole of the guide member. As a result, position alignment between the optical interface and the photoelectric wiring board is conducted with high precision.
    Type: Application
    Filed: October 7, 2005
    Publication date: April 13, 2006
    Applicant: NEC CORPORATION
    Inventors: Junichi Sasaki, Ichiro Hatakeyama, Kazunori Miyoshi, Hikaru Kouta, Kaichiro Nakano, Mikio Oda, Hisaya Takahashi, Mitsuru Kurihara
  • Patent number: 6583400
    Abstract: A multichannel receiver circuit is provided, which suppresses effectively crosstalk or interference between the electric signals transmitted in parallel through multiple channels at high speed and which improves the S/N for each channel. The receiver circuit comprises first to n-th sections for forming respectively first to n-th channels, where n is an integer greater than unity. The first to n-th sections receive first to n-th electric input signals to produce first to n-th electric output signals, respectively, where each of the first to n-th output signals having different logic levels according to a corresponding one of the first to n-th input signals. Each of the first to n-th sections includes an output level fixer circuit that produces an output signal. The output signal of the output level fixer circuit having a fixed level that induces no oscillation when a corresponding one of the first to n-th input signals has a level less than a specific reference level.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: June 24, 2003
    Assignee: NEC Corporation
    Inventor: Kazunori Miyoshi
  • Patent number: 6538790
    Abstract: An optical receiver array includes a plurality of light-receiving elements, a plurality of amplifiers, and a plurality of low-pass filters. The light-receiving elements convert optical signals of a plurality of channels into electrical signals, respectively. The amplifiers amplify the electrical signals output from the light-receiving elements and output the electrical signals. Each amplifier has positive and negative power supply terminals to which power is supplied. Each low-pass filter is connected between the positive power supply terminal of a corresponding amplifier and a first external power supply terminal or between the negative power supply terminal of a corresponding amplifier and a second external power supply terminal. Each light-receiving element is connected between the positive power supply terminal and an input terminal of a corresponding amplifier or between the input terminal and the negative power supply terminal of a corresponding amplifier.
    Type: Grant
    Filed: June 22, 1999
    Date of Patent: March 25, 2003
    Assignee: NEC Corporation
    Inventors: Ichiro Hatakeyama, Takeshi Nagahori, Kazunori Miyoshi
  • Publication number: 20020050558
    Abstract: A multichannel receiver circuit is provided, which suppresses effectively crosstalk or interference between the electric signals transmitted in parallel through multiple channels at high speed and which improves the S/N for each channel. The receiver circuit comprises first to n-th sections for forming respectively first to n-th channels, where n is an integer greater than unity. The first to n-th sections receive first to n-th electric input signals to produce first to n-th electric output signals, respectively, where each of the first to n-th output signals having different logic levels according to a corresponding one of the first to n-th input signals. Each of the first to n-th sections includes an output level fixer circuit that produces an output signal. The output signal of the output level fixer circuit having a fixed level that induces no oscillation when a corresponding one of the first to n-th input signals has a level less than a specific reference level.
    Type: Application
    Filed: October 31, 2001
    Publication date: May 2, 2002
    Inventor: Kazunori Miyoshi
  • Patent number: 6181454
    Abstract: In an optical receiver, a photodiode converts an optical digital input signal to an electrical signal which is fed into a differential amplifier to produce a pair of true and complementary output signals. The true output signal is received by a peak detector and the output of this peak detector is summed in a first adder with the complementary output of the differential amplifier. The true output of the amplifier is summed in a second adder with a predetermined constant voltage. Difference between the output signals of the first and second adders is detected and compared with a decision threshold to produce an output signal at one of two logical levels depending on whether the difference is higher or lower than the decision threshold. Preferably, a second peak detector having a substantially similar operating characteristic to that of the first peak detector is connected between the source of the predetermined constant voltage and the second adder.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: January 30, 2001
    Assignee: NEC Corporation
    Inventors: Takeshi Nagahori, Ichiro Hatakeyama, Kazunori Miyoshi