Patents by Inventor Kazunori Miyoshi
Kazunori Miyoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11915951Abstract: A plasma processing apparatus includes a stage disposed in a processing chamber for mounting a wafer, a plasma generation chamber disposed above the processing chamber for plasma generation using process gas, a plate member having multiple introduction holes, made of a dielectric material, disposed above the stage and between the processing chamber and the plasma generation chamber, and a lamp disposed around the plate member for heating the wafer. The plasma processing apparatus further includes an external IR light source, an emission fiber arranged in the stage, that outputs IR light from the external IR light source toward a wafer bottom, and a light collection fiber for collecting IR light from the wafer. Data obtained using only IR light from the lamp is subtracted from data obtained also using IR light from the external IR light source during heating of the wafer. Thus, a wafer temperature is determined.Type: GrantFiled: June 26, 2020Date of Patent: February 27, 2024Assignee: HITACHI HIGH-TECH CORPORATIONInventors: Hiroyuki Kobayashi, Nobuya Miyoshi, Kazunori Shinoda, Tatehito Usui, Naoyuki Kofuji, Yutaka Kouzuma, Tomoyuki Watanabe, Kenetsu Yokogawa, Satoshi Sakai, Masaru Izawa
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Publication number: 20220300833Abstract: A feature extraction device 80 includes a feature extraction unit 81 which extracts a feature indicated by time-series data by machine learning using a recurrence plot generated from the time-series data.Type: ApplicationFiled: September 6, 2019Publication date: September 22, 2022Applicant: NEC CorporationInventor: Kazunori MIYOSHI
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Patent number: 11032144Abstract: A network control system includes link design unit for deciding, as a configuration of one network formed by connecting a plurality of nodes having a communication function, a configuration of distributed networks included in the network and specific links for forming the network by connecting the distributed networks; and network configuration switching unit for switching the configuration of the network by logically enabling or disabling the specific links on request at least in a state where links other than the specific links are enabled, in which the link design unit decides the configuration of the distributed networks and the specific links based on a cluster hierarchical structure corresponding to a formation process of the one network which is formed as a result of sequentially adding links, which connect the nodes, based on a connection weight decided in accordance with a degree of spread or complexity of the network after connection.Type: GrantFiled: July 12, 2017Date of Patent: June 8, 2021Assignee: NEC CORPORATIONInventor: Kazunori Miyoshi
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Publication number: 20200195502Abstract: A network control system includes link design unit for deciding, as a configuration of one network formed by connecting a plurality of nodes having a communication function, a configuration of distributed networks included in the network and specific links for forming the network by connecting the distributed networks; and network configuration switching unit for switching the configuration of the network by logically enabling or disabling the specific links on request at least in a state where links other than the specific links are enabled, in which the link design unit decides the configuration of the distributed networks and the specific links based on a cluster hierarchical structure corresponding to a formation process of the one network which is formed as a result of sequentially adding links, which connect the nodes, based on a connection weight decided in accordance with a degree of spread or complexity of the network after connection.Type: ApplicationFiled: July 12, 2017Publication date: June 18, 2020Applicant: NEC CORPORATIONInventor: Kazunori MIYOSHI
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Patent number: 9742665Abstract: A communication network control system (1) eliminates, in a communication network (G) in which a plurality of nodes (Ni) are connected via a plurality of links (2), a node (Nx) having a trouble and implements a reconnection in the communication network (G).Type: GrantFiled: August 13, 2013Date of Patent: August 22, 2017Assignee: NEC CorporationInventor: Kazunori Miyoshi
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Publication number: 20150334007Abstract: A communication network control system (1) eliminates, in a communication network (G) in which a plurality of nodes (Ni) are connected via a plurality of links (2), a node (Nx) having a trouble and implements a reconnection in the communication network (G).Type: ApplicationFiled: August 13, 2013Publication date: November 19, 2015Applicant: NEC CorporationInventor: Kazunori MIYOSHI
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Patent number: 8493882Abstract: Provided is an optimization evaluation system, wherein the effect of the optimization of traffic characteristic in a communication network is quantitatively evaluated. An optimization evaluation system which evaluates effects of optimization done by an optimization function in a communication network that has the optimization function for optimizing a communication traffic characteristic, including: a communication traffic analyzing module which acquires a communication traffic variation distribution based on measured communication traffic data; and a communication traffic evaluation module which executes processing for quantitatively evaluating the effects of the optimization of the communication traffic characteristic executed by the optimization function based on a fact whether or not the variation distribution calculated by the communication traffic analyzing module is a power function.Type: GrantFiled: April 9, 2009Date of Patent: July 23, 2013Assignee: NEC CorporationInventor: Kazunori Miyoshi
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Publication number: 20110058498Abstract: Provided is an optimization evaluation system, wherein the effect of the optimization of traffic characteristic in a communication network is quantitatively evaluated. An optimization evaluation system which evaluates effects of optimization done by an optimization function in a communication network that has the optimization function for optimizing a communication traffic characteristic, including: a communication traffic analyzing module which acquires a communication traffic variation distribution based on measured communication traffic data; and a communication traffic evaluation module which executes processing for quantitatively evaluating the effects of the optimization of the communication traffic characteristic executed by the optimization function based on a fact whether or not the variation distribution calculated by the communication traffic analyzing module is a power function.Type: ApplicationFiled: April 9, 2009Publication date: March 10, 2011Inventor: Kazunori Miyoshi
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Patent number: 7783143Abstract: A semiconductor device has printed wiring board (11) where electric wiring (18) connected to LSI chip (17) and to planar optical element (21) is formed, and where optical waveguide (25) which transfers light inputted into planar optical element (21) and/or light outputted from planar optical element (21) is fixed. Planar optical element (21) is mounted in one end of small substrate (13), and another end of small substrate (13) is connected to printed wiring board (11) by solder bump (26). One end of small substrate (13) where planar optical element (21) is mounted is fixed to printed wiring board (11) by a fixing mechanism. Small substrate (13) has flexible section (15), which is easily deformable compared with other portions of printed wiring board (11) and small substrate (13), in at least a partial region between one end where planar optical element (21) is mounted and another end electrically connected to printed wiring board (11).Type: GrantFiled: April 3, 2009Date of Patent: August 24, 2010Assignee: NEC CorporationInventors: Kazunori Miyoshi, Kazuhiko Kurata, Takanori Shimizu, Ichiro Hatakeyama, Junichi Sasaki
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Publication number: 20090269078Abstract: A dispersion compensator (1) has a substrate (2) made of a resin, on which a conductor layer (3a), a dielectric layer (4a), a wiring layer (5a), a dielectric layer (4b), a wiring layer (5b), a dielectric layer (4c), and a conductor layer (3b) are provided in this order. A transmission line (6a) forming the wiring layer (5a) and a transmission line (6b) forming the wiring layer (5b) have identical shapes to each other and have equivalent dispersion characteristics to each other. The transmission lines (6a) and (6b) are formed in a meander shape and are arranged to overlap with each other as viewed in plan. Differential signals (14) and (15) are input to the transmission lines (6a) and (6b), respectively.Type: ApplicationFiled: February 16, 2006Publication date: October 29, 2009Inventor: Kazunori Miyoshi
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Patent number: 7561762Abstract: A semiconductor device has printed wiring board (11) where electric wiring (18) connected to LSI chip (17) and to planar optical element (21) is formed, and where optical waveguide (25) which transfers light inputted into planar optical element (21) and/or light outputted from planar optical element (21) is fixed. Planar optical element (21) is mounted in one end of small substrate (13), and another end of small substrate (13) is connected to printed wiring board (11) by solder bump (26). One end of small substrate (13) where planar optical element (21) is mounted is fixed to printed wiring board (11) by a fixing mechanism. Small substrate (13) has flexible section (15), which is easily deformable compared with other portions of printed wiring board (11) and small substrate (13), in at least a partial region between one end where planar optical element (21) is mounted and another end electrically connected to printed wiring board (11).Type: GrantFiled: September 20, 2005Date of Patent: July 14, 2009Assignee: NEC CorporationInventors: Kazunori Miyoshi, Kazuhiko Kurata, Takanori Shimizu, Ichiro Hatakeyama, Junichi Sasaki
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Patent number: 7473038Abstract: An optical connector according to the present invention including a connector body mounted on an optical module mounted on a circuit board, and a connector fixing member for pressing the connector body against the optical module. The connector fixing member can be engaged/disengaged with/from the circuit board, and thus the connector body can be attached/detached to/from the optical module.Type: GrantFiled: May 22, 2006Date of Patent: January 6, 2009Assignees: Fujikura Ltd., NEC CorporationInventors: Kunihiko Fujiwara, Akito Nishimura, Kenji Sasaki, Yukio Hayashi, Ichiro Hatakeyama, Youichi Hashimoto, Junichi Sasaki, Ryosuke Kuribayashi, Kazunori Miyoshi, Kazuhiko Kurata
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Patent number: 7333683Abstract: An LSI package having an optical interface is mounted on a surface of a photoelectric wiring board. The photoelectric wiring board and the optical interface are optically connected with sufficient precision. A wiring board side guide member including socket pins and guide pins is soldered and fixed onto the photoelectric wiring board including an optical transmission line, a guide pin, and a mirror. An optical interface side guide member having a fitting hole is glued to the optical interface. The optical interface is mounted on an interposer of the LSI package. The guide pin of the photoelectric wiring board is fitted into the fitting hole formed through the interposer. The guide pin of the guide member is fitted into the fitting hole of the guide member. As a result, position alignment between the optical interface and the photoelectric wiring board is conducted with high precision.Type: GrantFiled: October 7, 2005Date of Patent: February 19, 2008Assignee: NEC CorproationInventors: Junichi Sasaki, Ichiro Hatakeyama, Kazunori Miyoshi, Hikaru Kouta, Kaichiro Nakano, Mikio Oda, Hisaya Takahashi, Mitsuru Kurihara
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Publication number: 20080036021Abstract: A semiconductor device has printed wiring board (11) where electric wiring (18) connected to LSI chip (17) and to planar optical element (21) is formed, and where optical waveguide (25) which transfers light inputted into planar optical element (21) and/or light outputted from planar optical element (21) is fixed. Planar optical element (21) is mounted in one end of small substrate (13), and another end of small substrate (13) is connected to printed wiring board (11) by solder bump (26). One end of small substrate (13) where planar optical element (21) is mounted is fixed to printed wiring board (11) by a fixing mechanism. Small substrate (13) has flexible section (15), which is easily deformable compared with other portions of printed wiring board (11) and small substrate (13), in at least a partial region between one end where planar optical element (21) is mounted and another end electrically connected to printed wiring board (11).Type: ApplicationFiled: September 20, 2005Publication date: February 14, 2008Applicant: NEC CORPORATIONInventors: Kazunori Miyoshi, Kazuhiko Kurata, Takanori Shimizu, Ichiro Hatakeyama, Junichi Sasaki
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Publication number: 20060280410Abstract: An optical connector according to the present invention including a connector body mounted on an optical module mounted on a circuit board, and a connector fixing member for pressing the connector body against the optical module. The connector fixing member can be engaged/disengaged with/from the circuit board, and thus the connector body can be attached/detached to/from the optical module.Type: ApplicationFiled: May 22, 2006Publication date: December 14, 2006Inventors: Kunihiko Fujiwara, Akito Nishimura, Kenji Sasaki, Yukio Hayashi, Ichiro Hatakeyama, Youichi Hashimoto, Junichi Sasaki, Ryosuke Kuribayashi, Kazunori Miyoshi, Kazuhiko Kurata
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Publication number: 20060078248Abstract: An LSI package having an optical interface is mounted on a surface of a photoelectric wiring board. The photoelectric wiring board and the optical interface are optically connected with sufficient precision. A wiring board side guide member including socket pins and guide pins is soldered and fixed onto the photoelectric wiring board including an optical transmission line, a guide pin, and a mirror. An optical interface side guide member having a fitting hole is glued to the optical interface. The optical interface is mounted on an interposer of the LSI package. The guide pin of the photoelectric wiring board is fitted into the fitting hole formed through the interposer. The guide pin of the guide member is fitted into the fitting hole of the guide member. As a result, position alignment between the optical interface and the photoelectric wiring board is conducted with high precision.Type: ApplicationFiled: October 7, 2005Publication date: April 13, 2006Applicant: NEC CORPORATIONInventors: Junichi Sasaki, Ichiro Hatakeyama, Kazunori Miyoshi, Hikaru Kouta, Kaichiro Nakano, Mikio Oda, Hisaya Takahashi, Mitsuru Kurihara
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Patent number: 6583400Abstract: A multichannel receiver circuit is provided, which suppresses effectively crosstalk or interference between the electric signals transmitted in parallel through multiple channels at high speed and which improves the S/N for each channel. The receiver circuit comprises first to n-th sections for forming respectively first to n-th channels, where n is an integer greater than unity. The first to n-th sections receive first to n-th electric input signals to produce first to n-th electric output signals, respectively, where each of the first to n-th output signals having different logic levels according to a corresponding one of the first to n-th input signals. Each of the first to n-th sections includes an output level fixer circuit that produces an output signal. The output signal of the output level fixer circuit having a fixed level that induces no oscillation when a corresponding one of the first to n-th input signals has a level less than a specific reference level.Type: GrantFiled: October 31, 2001Date of Patent: June 24, 2003Assignee: NEC CorporationInventor: Kazunori Miyoshi
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Patent number: 6538790Abstract: An optical receiver array includes a plurality of light-receiving elements, a plurality of amplifiers, and a plurality of low-pass filters. The light-receiving elements convert optical signals of a plurality of channels into electrical signals, respectively. The amplifiers amplify the electrical signals output from the light-receiving elements and output the electrical signals. Each amplifier has positive and negative power supply terminals to which power is supplied. Each low-pass filter is connected between the positive power supply terminal of a corresponding amplifier and a first external power supply terminal or between the negative power supply terminal of a corresponding amplifier and a second external power supply terminal. Each light-receiving element is connected between the positive power supply terminal and an input terminal of a corresponding amplifier or between the input terminal and the negative power supply terminal of a corresponding amplifier.Type: GrantFiled: June 22, 1999Date of Patent: March 25, 2003Assignee: NEC CorporationInventors: Ichiro Hatakeyama, Takeshi Nagahori, Kazunori Miyoshi
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Publication number: 20020050558Abstract: A multichannel receiver circuit is provided, which suppresses effectively crosstalk or interference between the electric signals transmitted in parallel through multiple channels at high speed and which improves the S/N for each channel. The receiver circuit comprises first to n-th sections for forming respectively first to n-th channels, where n is an integer greater than unity. The first to n-th sections receive first to n-th electric input signals to produce first to n-th electric output signals, respectively, where each of the first to n-th output signals having different logic levels according to a corresponding one of the first to n-th input signals. Each of the first to n-th sections includes an output level fixer circuit that produces an output signal. The output signal of the output level fixer circuit having a fixed level that induces no oscillation when a corresponding one of the first to n-th input signals has a level less than a specific reference level.Type: ApplicationFiled: October 31, 2001Publication date: May 2, 2002Inventor: Kazunori Miyoshi
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Patent number: 6181454Abstract: In an optical receiver, a photodiode converts an optical digital input signal to an electrical signal which is fed into a differential amplifier to produce a pair of true and complementary output signals. The true output signal is received by a peak detector and the output of this peak detector is summed in a first adder with the complementary output of the differential amplifier. The true output of the amplifier is summed in a second adder with a predetermined constant voltage. Difference between the output signals of the first and second adders is detected and compared with a decision threshold to produce an output signal at one of two logical levels depending on whether the difference is higher or lower than the decision threshold. Preferably, a second peak detector having a substantially similar operating characteristic to that of the first peak detector is connected between the source of the predetermined constant voltage and the second adder.Type: GrantFiled: April 23, 1998Date of Patent: January 30, 2001Assignee: NEC CorporationInventors: Takeshi Nagahori, Ichiro Hatakeyama, Kazunori Miyoshi