Abstract: A number of micro-sized rectangular dot-like n-type semiconductor regions 121 are created in a p-type semiconductor region which is a base body 11. Contact parts 14, each of which is in contact with one n-type semiconductor region 121 and almost entirely covers the same region, are mutually connected by a wire part 15 as a common cathode terminal. The n-type semiconductor regions 121 receives no light; their function is to collect carriers generated within and outside the surrounding depletion layers. Appropriate setting of the spacing of the n-type semiconductor regions 121 enables efficient collection of the carriers generated in the p-type semiconductor region while improving the SN ratio of the photo-detection signal by a noise-reduction effect due to a decrease in the p-n junction capacitance. Carriers originating from light of shorter wavelengths are barely reflected in the photo-detection signal. Thus, unfavorable influences of the shorter wavelengths of light are eliminated.

Abstract: A number of micro-sized rectangular dot-like n-type semiconductor regions 121 are created in a p-type semiconductor region which is a base body 11. Contact parts 14, each of which is in contact with one n-type semiconductor region 121 and almost entirely covers the same region, are mutually connected by a wire part 15 as a common cathode terminal. The n-type semiconductor regions 121 receives no light; their function is to collect carriers generated within and outside the surrounding depletion layers. Appropriate setting of the spacing of the n-type semiconductor regions 121 enables efficient collection of the carriers generated in the p-type semiconductor region while improving the SN ratio of the photo-detection signal by a noise-reduction effect due to a decrease in the p-n junction capacitance. Carriers originating from light of shorter wavelengths are barely reflected in the photo-detection signal. Thus, unfavorable influences of the shorter wavelengths of light are eliminated.

Abstract: In one embodiment a signal conversion circuit includes; first hysteresis comparator configured to receive a differential signal having first and second input signal components, to compare in magnitude between voltages of the first and second input signal components, and to output the comparison result as a first output signal; a second hysteresis comparator configured to receive the first and second input signal components, to compare in magnitude between the voltages of the first and second input signal components, and to output the comparison result as a second output signal that is an inversion signal of the first output signal; and a conversion buffer configured to convert the first and second output signals into a single-end signal.

Abstract: A noncontact transmission device 100 is provided with a driver 106 for driving a coil 102; a system clock oscillator 110 for outputting a system clock; a monitoring clock oscillator 112 for outputting a monitoring clock LF0 having a frequency lower than that of the system clock CK0; and a control circuit 108. The control circuit 108 outputs a system clock oscillating control signal S60 based on the monitoring clock LF0 while being in a standby state and makes the system clock oscillator 110 intermittently output a system clock CK0 in synchronization with the control signal S60. In a period when the system clock CK0 is being outputted, the coil 102 is driven by a driver control signal SD and whether the device 200 to which data is to be transmitted is arranged or not is detected.

Abstract: A noncontact transmission device (100) is provided with a monitoring clock oscillator (112) for outputting a monitoring clock (LF0) having a frequency lower than that of a system clock (CK0); a control circuit (108); a memory (114) having information (D) stored to be used by the control circuit (108); and a reset circuit (116). The control circuit (108) includes an internal storage circuit for storing the information (D) read out from the memory (114). The control circuit (108) reads out and updates the information (D) stored in the internal storage circuit from the memory (114) with an update period based on the monitoring clock (LF0). Furthermore, the control circuit (108) is reset with a reset period longer than the update period based on the monitoring clock (LF0), and, each time the control circuit (108) is reset, reads out the information (D) from the memory (114) and updates the information (D) stored in the internal storage circuit.

Abstract: A noncontact transmission device (100) is provided with a monitoring clock oscillator (112) for outputting a monitoring clock (LF0) having a frequency lower than that of a system clock (CK0); a control circuit (108); a memory (114) having information (D) stored to be used by the control circuit (108); and a reset circuit (116). The control circuit (108) includes an internal storage circuit for storing the information (D) read out from the memory (114). The control circuit (108) reads out and updates the information (D) stored in the internal storage circuit from the memory (114) with an update period based on the monitoring clock (LF0). Furthermore, the control circuit (108) is reset with a reset period longer than the update period based on the monitoring clock (LF0), and, each time the control circuit (108) is reset, reads out the information (D) from the memory (114) and updates the information (D) stored in the internal storage circuit.

Abstract: A noncontact transmission device 100 is provided with a driver 106 for driving a coil 102; a system clock oscillator 110 for outputting a system clock; a monitoring clock oscillator 112 for outputting a monitoring clock LF0 having a frequency lower than that of the system clock CK0; and a control circuit 108. The control circuit 108 outputs a system clock oscillating control signal S60 based on the monitoring clock LF0 while being in a standby state and makes the system clock oscillator 110 intermittently output a system clock CK0 in synchronization with the control signal S60. In a period when the system clock CK0 is being outputted, the coil 102 is driven by a driver control signal SD and whether the device 200 to which data is to be transmitted is arranged or not is detected.

Abstract: A power circuit outputs and applies an AC voltage and a DC voltage to respective terminals of a capacitor, so as to obtain an AC output voltage shifted in accordance with the DC voltage component. The power circuit comprises a first voltage adjuster for outputting an AC voltage and a first DC voltage, and a second voltage adjuster for outputting a second DC voltage. For a predetermined duration after turning on power, the power circuit supplies the first DC voltage from the first voltage adjuster and the second DC voltage from the second voltage adjuster, for application to respective terminals of the capacitor. After the predetermined duration has passed, the power circuit changes the voltage output from the first voltage adjuster to the AC voltage, and supplies the AC voltage and the second DC voltage for application to the respective terminals of the capacitor. With this arrangement, a required potential can be quickly achieved at the time of turning on power.

Abstract: A power circuit outputs and applies an AC voltage and a DC voltage to respective terminals of a capacitor, so as to obtain an AC output voltage shifted in accordance with the DC voltage component. The power circuit includes a first voltage adjuster for outputting an AC voltage, a second voltage adjuster for outputting a DC voltage, a first output terminal which outputs the AC voltage from the first voltage adjuster, and a second output terminal which outputs the DC voltage from the second voltage adjuster. The first output terminal is connected to one end of the capacitor, while the second output terminal is connected to the other end of the capacitor. The power circuit controls impedance between the first output terminal and the first voltage adjuster.

Abstract: A power circuit outputs and applies an AC voltage and a DC voltage to respective terminals of a capacitor, so as to obtain an AC output voltage shifted in accordance with the DC voltage component. The power circuit comprises a first voltage adjuster for outputting an AC voltage and a first DC voltage, and a second voltage adjuster for outputting a second DC voltage. For a predetermined duration after turning on power, the power circuit supplies the first DC voltage from the first voltage adjuster and the second DC voltage from the second voltage adjuster, for application to respective terminals of the capacitor. After the predetermined duration has passed, the power circuit changes the voltage output from the first voltage adjuster to the AC voltage, and supplies the AC voltage and the second DC voltage for application to the respective terminals of the capacitor. With this arrangement a required potential can be quickly achieved at the time of turning on power.

Abstract: A power circuit outputs and applies an AC voltage and a DC voltage to respective terminals of a capacitor, so as to obtain an AC output voltage shifted in accordance with the DC voltage component. The power circuit comprises a first voltage adjuster for outputting an AC voltage, a second voltage adjuster for outputting a DC voltage, a first output terminal which outputs the AC voltage from the first voltage adjuster, and a second output terminal which outputs the DC voltage from the second voltage adjuster. The first output terminal is connected to one end of the capacitor, while the second output terminal is connected to the other end of the capacitor.

Abstract: The present invention provides a dual band transmitting/receiving device, which can perform transmission and diversity reception with low insertion loss in that the number of switches for switching antennas is small. The dual band transmitting/receiving device is constituted such that transmitting/receiving dual band antennas 1 and 2 capable of being used in both of 5 GHz band used with IEEE 802.11a communication standard and 2.4 GHz band used with IEEE 802.11b communication standard are connected to respective transmitting circuits 7 and 9 and respective receiving circuits 8 and 10 used with respective communication standards, in a state where the above each signaling path between the each antenna and the each receiving circuit or transmitting circuit is connected via the only one switch.

Abstract: A liquid crystal drive circuit for charging video signals to an active matrix type liquid crystal panel as two AC signals in relation to polarity inversion of an opposed electrode, characterized in that it is provided with an amplifier for delivering an inverted video signal and a non-inverted video signal and with a mixer circuit for offsetting AC components by mixing the inverted video signal and said non-inverted video signal, thereby regulating a DC level of said amplifier on the basis of an output signal from the mixer circuit.

Abstract: A Y/C separation circuit includes a glass delay line for delaying an input composite video signal. A luminance signal and a chrominance signal are separated from each other by an adding circuit and a subtracting circuit each of which receives the input signal and an output signal from the glass delay line. The output signal from the glass delay line is phase-shifted by a 90.degree. phase shifting circuit and then inputted to a multiplier which further receives the input signal. The multiplier outputs an error signal according to a phase difference between color burst signals included in the both signals, and a control voltage according to the error signal is outputted from a low-pass filter. The control voltage is applied to gyrators which terminate an input and an output of the glass delay line, respectively, whereby an inductance value of each of the gyrators is controlled by the control voltage such that a delay time of the glass delay line can be exactly adjusted at one horizontal period.

Abstract: A holding circuit used in a pedestal level clamp circuit of a color television receiver. By using base current of a transistor as charging current of a capacitor, a large time constant is obtained. Also, in case the voltage lower than the reference voltage is held, base current of the transistor is used as discharging current to discharge slowly. Furthermore, though a charging transistor of the capacitor must be a PNP type and a discharging transistor must be an NPN type, it is designed not to be influenced by the difference in current amplification factors of the two types.

Abstract: A direct current restorer applied to a pedestal clamp circuit of a television receiver in which an input video signal is compared with a pedestal level setting reference signal for every pedestal period, and, based on difference between the pedestal level of the input video signal and the level of the reference signal, the direct current level of the input video signal is shifted. In this direct current restorer, a direct current according to the level variation of the reference signal may be superposed on the input video signal so that the direct current level of the input video signal is corrected according to the level variation of the reference signal. Accordingly, when adjusting the pedestal level or achieving a liquid crystal display in which the polarity of the input video signal is periodically inverted, a direct current according to the level variation of the reference signal may be superposed on the input video signal.

Abstract: A peak holding circuit comprises a capacitor for holding signal charges corresponding to a peak level of an input signal, and a current amplifier circuit comprising transistors connected in a triple darlington manner for supplying an output current corresponding to the held charges. An emitter of a transistor in the first stage out of the transistors connected in a darlington manner is connected to a collector of another transistor through which a collector cut-off current flows which is approximately equal to a collector cut-off current flowing through the transistor in the first stage. The other transistor has its emitter connected to ground. Therefore, the collector cut-off current flowing through the transistor in the first stage is cancelled, so that fluctuations in output current can be prevented even if a large reactive current is not allowed to flow through a transistor in the final stage out of the transistors connected in a darlington manner.

Abstract: A scrambling system of television signal includes a circuit for eliminating vertical sync pulses in a vertical sync pulse period and equivalent pulses in first and second equivalent pulse periods at opposite ends of said vertical sync pulse period. In place of the eliminated pulses, substitute pulses having a frequency equal to an integer times the frequency of horizontal sync pulses are deposited. A framing code inserting circuit is provided for inserting at least one framing code in the substituted pulses. The framing code is carrying information how the television signal is scrambled.