Patents by Inventor Kazunori Saitoh
Kazunori Saitoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8089819Abstract: A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.Type: GrantFiled: August 16, 2010Date of Patent: January 3, 2012Assignee: Renesas Electronics CorporationInventors: Hideyuki Noda, Kazunori Saitoh, Kazutami Arimoto, Katsumi Dosaka
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Publication number: 20100308858Abstract: A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.Type: ApplicationFiled: August 16, 2010Publication date: December 9, 2010Applicant: Renesas Technology Corp.Inventors: Hideyuki NODA, Kazunori Saitoh, Kazutami Ariomoto, Katsumi Dosaka
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Patent number: 7791962Abstract: A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.Type: GrantFiled: June 16, 2008Date of Patent: September 7, 2010Assignee: Renesas Technology Corp.Inventors: Hideyuki Noda, Kazunori Saitoh, Kazutami Ariomoto, Katsumi Dosaka
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Patent number: 7720127Abstract: An opto-semiconductor device. An opto-semiconductor element includes a semiconductor substrate, a multilayered semiconductor layer formed on a first surface of the semiconductor substrate and having a resonator, a first electrode with multiple conductive layers formed on the multilayered semiconductor layer, and a second electrode formed on a second surface of the semiconductor substrate. A support substrate has a first surface formed with a fixing portion having a conductive layer for fixing the first electrode connected thereto through a bonding material. Bonding material and conductive layers forming the first electrode react to form a reaction layer. The difference in thermal expansion coefficient between semiconductor substrate and support substrate is not more than ±50%. A second barrier metal layer not reactive with bonding material is formed inside the first electrode uppermost conductive layer, while uppermost layer reacts with the bonding material to form the reaction layer.Type: GrantFiled: September 22, 2008Date of Patent: May 18, 2010Assignee: OpNext Japan, Inc.Inventors: Yutaka Inoue, Kazunori Saitoh, Hiroshi Hamada, Masato Hagimoto, Susumu Sorimachi
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Patent number: 7674391Abstract: It is an objective to control the occurrence of the disorder of a far-field pattern and of an optical axial shift. A manufacturing method of a semiconductor laser device has the step for preparing a semiconductor substrate which has growth of a multi-layer including an active layer, the step for forming a mask over the growth of a multi-layer, and a step for forming a stripe-shaped ridge by dry etching and wet etching. A structure stacking a p-type AlGaInP layer, an etch-stop layer, a p-type Alx=0.7GaInP layer, a p-type Alx=0.6GaInP layer, a p-type GaAs layer, in order, over the active layer is taken in order to make the tailing part created in the dry etching process smaller by wet etching. The tailing part is composed of a p-type Alx=0.7GaInP layer including a high mixed crystal ratio of aluminum. Therefore, the p-type Alx=0.7GaInP layer is etched faster than the p-type Alx=0.Type: GrantFiled: January 31, 2007Date of Patent: March 9, 2010Assignee: Opnext Japan, Inc.Inventors: Hiroshi Hamada, Kazunori Saitoh
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Patent number: 7562198Abstract: A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.Type: GrantFiled: June 9, 2005Date of Patent: July 14, 2009Assignee: Renesas Technology Corp.Inventors: Hideyuki Noda, Kazunori Saitoh, Kazutami Ariomoto, Katsumi Dosaka
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Publication number: 20090041076Abstract: An opto-semiconductor device. An opto-semiconductor element includes a semiconductor substrate, a multilayered semiconductor layer formed on a first surface of the semiconductor substrate and having a resonator, a first electrode with multiple conductive layers formed on the multilayered semiconductor layer, and a second electrode formed on a second surface of the semiconductor substrate. A support substrate has a first surface formed with a fixing portion having a conductive layer for fixing the first electrode connected thereto through a bonding material. Bonding material and conductive layers forming the first electrode react to form a reaction layer. The difference in thermal expansion coefficient between semiconductor substrate and support substrate is not more than 50%. A second barrier metal layer not reactive with bonding material is formed inside the first electrode uppermost conductive layer, while uppermost layer reacts with the bonding material to form the reaction layer.Type: ApplicationFiled: September 22, 2008Publication date: February 12, 2009Inventors: Yutaka Inoue, Kazunori Saitoh, Hiroshi Hamada, Masato Hagimoto, Susumu Sorimachi
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Publication number: 20090027978Abstract: A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.Type: ApplicationFiled: June 16, 2008Publication date: January 29, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hideyuki Noda, Kazunori Saitoh, Kazutami Ariomoto, Katsumi Dosaka
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Patent number: 7463662Abstract: A highly reliable optical semiconductor device insusceptible to degradation in the characteristics thereof. An n-type buffer layer, n-type first cladding layer, active layer, a p-type first layer of the second cladding layer, p-type etch-stop layer, p-type second layer of the second cladding layer, and p-type contact layer are formed an n-type semiconductor substrate. Two lengths of separation grooves are formed in parallel in such a way as to reach the underside of the p-type second layer of the second cladding layer from the top face of the contact layer, and a ridge is formed between the respective separation grooves. The ridge comprises a lower portion thereof, made up of the second layer of the second cladding layer, and a portion of the contact layer, corresponding to the ridge, made up of the contact layer.Type: GrantFiled: February 8, 2006Date of Patent: December 9, 2008Assignee: Opnext Japan, Inc.Inventors: Kazunori Saitoh, Hiroshi Hamada
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Patent number: 7443901Abstract: An opto-semiconductor device. An opto-semiconductor element includes a semiconductor substrate, a multilayered semiconductor layer formed on a first surface of the semiconductor substrate and having a resonator, a first electrode with multiple conductive layers formed on the multilayered semiconductor layer, and a second electrode formed on a second surface of the semiconductor substrate. A support substrate has a first surface formed with a fixing portion having a conductive layer for fixing the first electrode connected thereto through a bonding material. Bonding material and conductive layers forming the first electrode react to form a reaction layer. The difference in thermal expansion coefficient between semiconductor substrate and support substrate is not more than ±50%. A second barrier metal layer not reactive with bonding material is formed inside the first electrode uppermost conductive layer, while uppermost layer reacts with the bonding material to form the reaction layer.Type: GrantFiled: March 24, 2006Date of Patent: October 28, 2008Assignee: OpNext Japan, Inc.Inventors: Yutaka Inoue, Kazunori Saitoh, Hiroshi Hamada, Masato Hagimoto, Susumu Sorimachi
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Publication number: 20070284336Abstract: It is an objective to control the occurrence of the disorder of a far-field pattern and of an optical axial shift. A manufacturing method of a semiconductor laser device has the step for preparing a semiconductor substrate which has growth of a multi-layer including an active layer, the step for forming a mask over the growth of a multi-layer, and a step for forming a stripe-shaped ridge by dry etching and wet etching. A structure stacking a p-type AlGaInP layer, an etch-stop layer, a p-type Alx=0.7GaInP layer, a p-type Alx=0.6GaInP layer, a p-type GaAs layer, in order, over the active layer is taken in order to make the tailing part created in the dry etching process smaller by wet etching. The tailing part is composed of a p-type Alx=0.7GaInP layer including a high mixed crystal ratio of aluminum. Therefore, the p-type Alx=0.7GaInP layer is etched faster than the p-type Alx=0.Type: ApplicationFiled: January 31, 2007Publication date: December 13, 2007Inventors: Hiroshi Hamada, Kazunori Saitoh
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Publication number: 20060222031Abstract: An opto-semiconductor device. An opto-semiconductor element includes a semiconductor substrate, a multilayered semiconductor layer formed on a first surface of the semiconductor substrate and having a resonator, a first electrode with multiple conductive layers formed on the multilayered semiconductor layer, and a second electrode formed on a second surface of the semiconductor substrate. A support substrate has a first surface formed with a fixing portion having a conductive layer for fixing the first electrode connected thereto through a bonding material. Bonding material and conductive layers forming the first electrode react to form a reaction layer. The difference in thermal expansion coefficient between semiconductor substrate and support substrate is not more than ±50%. A second barrier metal layer not reactive with bonding material is formed inside the first electrode uppermost conductive layer, while uppermost layer reacts with the bonding material to form the reaction layer.Type: ApplicationFiled: March 24, 2006Publication date: October 5, 2006Inventors: Yutaka Inoue, Kazunori Saitoh, Hiroshi Hamada, Masato Hagimoto, Susumu Sorimachi
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Publication number: 20060222030Abstract: A highly reliable optical semiconductor device insusceptible to degradation in the characteristics thereof. An n-type buffer layer, n-type first cladding layer, active layer, a p-type first layer of the second cladding layer, p-type etch-stop layer, p-type second layer of the second cladding layer, and p-type contact layer are formed an n-type semiconductor substrate. Two lengths of separation grooves are formed in parallel in such a way as to reach the underside of the p-type second layer of the second cladding layer from the top face of the contact layer, and a ridge is formed between the respective separation grooves. The ridge comprises a lower portion thereof, made up of the second layer of the second cladding layer, and a portion of the contact layer, corresponding to the ridge, made up of the contact layer.Type: ApplicationFiled: February 8, 2006Publication date: October 5, 2006Inventors: Kazunori Saitoh, Hiroshi Hamada
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Publication number: 20060004723Abstract: A method for reading tag data is provided, involving reading a compressed data file that includes compressed data and tag data of a fixed length appended to the compressed data at a predetermined position, and performing a predetermined process based on the type of the compressed data. The reading process of the compressed data file includes first searching for the starting position of the tag data of the compressed data file and retrieving the tag data, followed by searching for the starting position of the compressed data.Type: ApplicationFiled: May 27, 2005Publication date: January 5, 2006Inventors: Akihito Fujiwara, Seiji Nakano, Masakazu Takahashi, Hiroyuki Akama, Kazunori Saitoh, Kazushige Kawana, Akihiro Hashimoto
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Publication number: 20050285862Abstract: A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.Type: ApplicationFiled: June 9, 2005Publication date: December 29, 2005Inventors: Hideyuki Noda, Kazunori Saitoh, Kazutami Ariomoto, Katsumi Dosaka
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Patent number: 6835543Abstract: An immunoassay for detecting an antigen in a sample, by: (a) sequentially contacting the sample with (i) a first antibody which is capable of specifically binding to a first binding site on the antigen, and then (ii) a second antibody which is capable of specifically binding to a second binding site on the antigen, thereby forming, when the antigen is present in the sample, an agglutinate comprising the first antibody, the antigen, and the second antibody; followed by (b) optically measuring the amount of the agglutinate.Type: GrantFiled: July 11, 1997Date of Patent: December 28, 2004Assignee: Daiichi Pure Chemicals Co., Ltd.Inventors: Kazunori Saitoh, Mitsuhisa Manabe
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Patent number: 6631062Abstract: An electrically conductive ceramics comprises a compound containing at least one element belonging to the Group 3A of the periodic table and TiO2−x (0<x<2) in a range such that the TiO2−x (0<x<2) accounts for 1 to 60 wt % of the total amount of the ceramics, and at least part of the compound and the TiO2−x form a composite oxide.Type: GrantFiled: December 6, 1999Date of Patent: October 7, 2003Assignees: Nihon Ceratec Co., Ltd., Taiheiyo Cement CorporationInventors: Kazuyoshi Minamisawa, Hiroyuki Matsuo, Sari Endoh, Yukio Kishi, Kazunori Saitoh, Hiroshi Suzuki, Motohiro Umezu, Mamoru Ishii, Hironori Ishida, Youichi Shirakawa, Norikazu Sashida
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Patent number: 6563774Abstract: An apparatus for carrying out a fine servo control and a rough servo control with respect to the rotation of a motor for rotating a recording medium in accordance with information recorded on the recording medium. A fine servo signal is generated on the basis of a reproduction clock, filtered by a first filtering device, and used for the fine servo control. A rough servo signal is generated on the basis of a frame synchronizing signal, filtered by a second filtering device, and used for the rough servo control. The first filtering device has a first frequency band, and the second filtering device has a second frequency band. The upper limit of the second frequency band is lower than that of the first frequency band.Type: GrantFiled: November 18, 1999Date of Patent: May 13, 2003Assignees: Pioneer Corporation, Tohoku Pioneer CorporationInventors: Kazuhiro Kiyoura, Toshiyuki Suzuki, Takeshi Matsumoto, Takehiro Takada, Hiroshi Kitagawa, Kazunori Saitoh, Hiroyuki Abe
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Publication number: 20010007774Abstract: Disclosed herein is an immunoassay comprising reacting an immobilized antibody obtained by holding an antibody, which recognizes a part of an objective antigen of determination, on insoluble carrier particles with an antigen in a test specimen, then reacting a free antibody, which recognizes an antigen site different from that recognized by the immobilized antibody, with the antigen; or reacting a free antibody, which recognizes a part of an objective antigen of determination, with an antigen in a test specimen, then reacting an immobilized antibody obtained by holding an antibody, which recognizes an antigen site different from that recognized by the free antibody, on insoluble carrier particles with the antigen, and optically determining the degree of a change in agglutination occurred by the reaction.Type: ApplicationFiled: July 11, 1997Publication date: July 12, 2001Inventors: KAZUNORI SAITOH, MITSUHISA MANABE
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Patent number: 6192011Abstract: A gain controlling apparatus is provided with: an adjusting device (6, 7, 8) for adjusting a gain of a generation signal, which is generated on the basis of a light reception signal obtained by receiving a reflection light of a light beam from an information recording medium (1); and a detecting device (21, 14, 16) for detecting whether or not the generation signal is generated and outputting a detection signal when the generation signal is generated. The gain controlling apparatus is also provided with a controlling device (18) for controlling the adjusting device to increase the gain by a predetermined value set in advance when the detection signal is not outputted by the detecting device.Type: GrantFiled: November 19, 1999Date of Patent: February 20, 2001Assignees: Pioneer Corporation, Tohoku Pioneer CorporationInventors: Kazuhiro Kiyoura, Toshiyuki Suzuki, Takeshi Matsumoto, Hiroshi Kitagawa, Takehiro Takada, Kazunori Saitoh