Patents by Inventor Kazuo Hagimura

Kazuo Hagimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5304819
    Abstract: The present invention relates to a light-activated semiconductor device comprising light-emitting elements for emitting light respectively, light-receiving elements for producing driving voltages in response to the light respectively and output elements activated in response to the driving voltages respectively. The light-receiving elements are disposed on two planes opposed to each other. The output elements are disposed on their corresponding planes in opposing relationship.
    Type: Grant
    Filed: June 25, 1993
    Date of Patent: April 19, 1994
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hiroyasu Torazawa, Kenji Mizuuchi, Kazuo Hagimura
  • Patent number: 4489340
    Abstract: A PNPN semiconductor switch including an N type semiconductor substrate, spaced apart first and second P type diffused regions formed on a surface of an N type substrate, spaced apart first and second N type diffused regions formed in the second P type diffused region, a first gate insulating layer formed on the surface of the second P type diffused region between the first and second N type diffused regions to cover portions thereof, a first gate electrode formed on the first gate insulating layer between the first and second N type diffused regions, a resistance region disposed on the first gate insulating layer, one end of the resistance region on the side opposite to the first gate electrode, a second gate insulating layer overlying the first gate electrode and the resistance region, a semiinsulating layer formed on the surface of the substrate except over the first and second P type diffused regions, an insulating layer overlying the semiinsulating layer, a P gate electrode electrically connected to the
    Type: Grant
    Filed: January 28, 1981
    Date of Patent: December 18, 1984
    Assignees: Nippon Telegraph & Telephone Public Corporation, Oki Electric Industry Co., Ltd.
    Inventors: Jun Ueda, Haruo Mori, Kazuo Hagimura, Hirokazu Tsukada, Kotaro Kato
  • Patent number: 4244000
    Abstract: A circuit for preventing a dV/dt erroneous operation of a PNPN semiconductor switch is replaced by a capacitance on the surface of a semiconductor substrate, a high resistance gate electrode. In other words, such a circuit is formed on the surface of the substrate by a slight modification of the basic design without decreasing the chip area and without isolating component elements.
    Type: Grant
    Filed: November 20, 1979
    Date of Patent: January 6, 1981
    Assignees: Nippon Telegraph and Telephone Public Corporation, Oki Electric Industry Company, Ltd.
    Inventors: Jun Ueda, Haruo Mori, Kazuo Hagimura, Kotaro Kato