Patents by Inventor Kazuo Kihara

Kazuo Kihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5319235
    Abstract: A composite semiconductor element includes a semiconductor substrate having a single crystal region projecting in the form of an island, an epitaxial growth layer formed on the semiconductor substrate so as to surround the single crystal region, an insulating isolation layer formed in predetermined regions of the epitaxial growth layer, of the single crystal region, and of the semiconductor substrate so as to insulate/isolate the epitaxial growth layer and the single crystal region from each other and to form a plurality of island-like element regions in the epitaxial growth layer and in the single crystal region, an n-channel MOS transistor and a CCD element respectively formed in element regions in the single crystal region, and a p-channel MOS transistor and a bipolar element respectively formed in element regions in the epitaxial growth layer.
    Type: Grant
    Filed: August 13, 1992
    Date of Patent: June 7, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Kihara, Hiroyuki Nakazawa
  • Patent number: 5286986
    Abstract: In a semiconductor device, a charge transfer device, a bipolar transistor, and a MOSFET are formed on a single chip, and the peripheral portion of the charge transfer device is surrounded by an N.sup.+ -type region. Since the charge transfer device block is surrounded by the N.sup.+ -type region and the N.sup.+ -type buried layer, leaked charge of clocks from the charge transfer device is absorbed by the N.sup.+ -type region and the N.sup.+ -type buried layer.
    Type: Grant
    Filed: February 18, 1992
    Date of Patent: February 15, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Kihara, Minoru Taguchi
  • Patent number: 5220190
    Abstract: A semiconductor device according to the present invention has a semiconductor body of a first conductivity type, three islands of a second conductivity type, formed in the surface of the semiconductor body. Two wells of the first conductivity are formed in the first and second islands. The device further has a charge transfer device which back gate is formed of the first well, an insulated-gate FET of the first conductivity type which back gate is formed of the second island, an insulated-gate FET of the second conductivity type which back gate is formed of the second well, and a bipolar transistor which collector is formed of the third island. The first island surrounds the first well which serves as back gate of the charge transfer device, and blocks the noise generated in the first well. Hence, the other islands are free from the influence of the noise.
    Type: Grant
    Filed: January 16, 1991
    Date of Patent: June 15, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Minoru Taguchi, Kazuo Kihara
  • Patent number: 4994888
    Abstract: A semiconductor device comprising a semiconductor chip formed of a substrate of a first conductivity type and an epitaxial layer of the first conductivity type formed on the substrate, a charge transfer device section formed in the epitaxial layer and driven by a given clock, and a preset region of a second conductivity type formed adjacent to the charge transfer device section in the semiconductor ship. The preset region includes a first layer of the second conductivity type formed in a boundary portion between the substrate and the epitaxial layer, a second layer of the second conductivity type formed on the first layer the epitaxial layer, and a third layer of the second conductivity type formed on the second layer in the epitaxial layer to reach the surface of the substrate. The maximum value of the second conductivity type impurity concentration of the third layer is set smaller than the maximum value of the second conductivity type impurity concentration of the first layer.
    Type: Grant
    Filed: May 18, 1990
    Date of Patent: February 19, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Minoru Taguchi, Kazuo Kihara
  • Patent number: 4443808
    Abstract: A semiconductor device having a high breakdown voltage transistor and a Schottky barrier diode. The Schottky barrier diode is formed in a surface portion of a semiconductor layer adjacent to the base region of the transistor, and a well layer of the same conductivity type as and of a lower impurity concentration that of the aforementioned semiconductor layer is formed under the Schottky barrier diode.
    Type: Grant
    Filed: April 2, 1982
    Date of Patent: April 17, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kazuo Kihara, Masashi Ikeda
  • Patent number: 4428066
    Abstract: A semiconductor fused programmable read only memory having a fuse resistor formed on an insulator film of the surface of a substrate. An island region having a conductivity opposite to that of the surrounding region is formed below the fuse resistor for avoiding excess current flow through the substrate.
    Type: Grant
    Filed: April 22, 1981
    Date of Patent: January 24, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kazuo Kihara, Masashi Ikeda
  • Patent number: 4190949
    Abstract: Disclosed is a method for manufacturing a semiconductor device which comprises the steps of forming a first insulating film on a semiconductor substrate of one conductivity type which forms a collector region, boring an opening through the first insulating film to expose part of the substrate, forming a semiconductor layer on the exposed surface of the substrate and the first insulating film, forming a base-collector junction by introducing an impurity of the other conductivity type into the semiconductor layer, selectively removing the semiconductor layer to leave a semiconductor region consecutively connected to the exposed surface on the first insulating film, covering the semiconductor region with a second insulating film, and boring an opening through the second insulating film and introducing through the opening an impurity of the one conductivity type into the semiconductor region, whereby an emitter region is formed.
    Type: Grant
    Filed: November 14, 1978
    Date of Patent: March 4, 1980
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Masashi Ikeda, Kazuo Kihara