Abstract: This invention provides a placement area with an enlarged bump pitch while avoiding the risk of underfill void generation in the bump process. The number of bumps is not changed, but the bump pitch at the center is arranged in parallel with the drying direction of the flip-chip process in the drying direction, and an arrangement area in which n rows are enlarged by +b(?m) bump pitch is made, and the chip area is finely adjusted. According to the invention, with respect to the dry air direction after flux cleaning, the power of the dry air does not change for creating a minute bump enlarged area parallel to the air in the central portion.

Abstract: A state of a user of a mobile terminal having a display for displaying an image may be estimated. A sightline detector detects a sightline of the user of a mobile terminal and processing circuitry is configured to estimate a state of the user. The processing circuitry is configured to determine a top-down index value that is correlated with an attention source amount allocated to top-down attention of the user with respect to an image displayed on a display of the mobile terminal. The processing circuitry is configured to determine a bottom-up index value correlated with the attention source amount allocated to bottom-up attention of the user with respect to the image displayed on the display. The processing circuitry is configured to estimate the user state including an attention function degraded state based on the top-down index value and the bottom-up index value.

Abstract: A state of a user of a mobile terminal having a display for displaying an image maybe estimated. A sightline detector detects a sightline of the user of a mobile terminal and processing circuitry is configured to estimate a state of the user. The processing circuitry is configured to determine a top-down index value that is correlated with an attention source amount allocated to top-down attention of the user with respect to an image displayed on a display of the mobile terminal. The processing circuitry is configured to determine a bottom-up index value correlated with the attention source amount allocated to bottom-up attention of the user with respect to the image displayed on the display. The processing circuitry is configured to estimate the user state including an attention function degraded state based on the top-down index value and the bottom-up index value.

Abstract: A state of a user of a mobile terminal having a display for displaying an image may be estimated. A sightline detection detector detects a user's sightline of a mobile terminal that has a display for displaying an image. Processing circuitry is configured to estimate a state of the user including an attention function degraded state based on motion of the user's sightline with respect to the image displayed on the display of the mobile terminal.

Abstract: According to one embodiment, a semiconductor device includes a shallow P-well, a shallow N-well, a shallow P-well, and a shallow N-well formed in regions different from one another, a deep N-well formed in a part deeper than the shallow P-well and the shallow N-well, and a base material, and further includes a first transistor formed in a part of the shallow P-well and the shallow N-well on the side of the principal surface, and a second transistor formed in a part of the shallow P-well and the shallow N-well on the side of the principal surface, in which the shallow N-well is formed in such a way as to surround the peripheral edge of the region of the shallow P-well.

Abstract: According to one embodiment, a semiconductor device includes a shallow P-well, a shallow N-well, a shallow P-well, and a shallow N-well formed in regions different from one another, a deep N-well formed in a part deeper than the shallow P-well and the shallow N-well, and a base material, and further includes a first transistor formed in a part of the shallow P-well and the shallow N-well on the side of the principal surface, and a second transistor formed in a part of the shallow P-well and the shallow N-well on the side of the principal surface, in which the shallow N-well is formed in such a way as to surround the peripheral edge of the region of the shallow P-well.

Abstract: The cement clinker production system includes: a first supplying section configured to supply a sulfur source and a fluorine source of mineralizer; a second supplying device configured to supply clinker raw material; a crusher configured to crush the mixed raw material obtained by mixing the clinker raw material with the fluorine source of the mineralizer; a kiln configured to burn the crushed mixed raw material; an introducing section configured to introduce the sulfur source of the mineralizer to the kiln; a third supplying section configured to supply fuel to the kiln; and a test sample-analyzing system configured to collect each of the mixed raw material before the burning and the clinker after the burning and to measure amounts of the fluorine, main components and free lime depending on the type collected.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract: The purpose of the present invention is, when treating circulatory disease such as acute myocardial infarction, to correct a reduction in myocardial contractility and thereby prevent arrhythmia and the like, as well as to reduce infarct size. Provided is a neurostimulation device having a stimulus application part configured so as to apply a stimulus to a cervical or thoracic vagus nerve portion in a human or an animal, and a stimulus regulation part configured so as to regulate the quantity of stimulus applied from the stimulus application part to the vagus nerve portion. The stimulus regulation part establishes a quantity of stimulus that is less than a value at which adverse effects would be produced, determines the heart rate and R wave interval of the human or animal, and controls the quantity of stimulus on the basis of these determinations.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.

Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract: The cement clinker production system includes: a first supplying section configured to supply a sulfur source and a fluorine source of mineralizer; a second supplying device configured to supply clinker raw material; a crusher configured to crush the mixed raw material obtained by mixing the clinker raw material with the fluorine source of the mineralizer; a kiln configured to burn the crushed mixed raw material; an introducing section configured to introduce the sulfur source of the mineralizer to the kiln; a third supplying section configured to supply fuel to the kiln; and a test sample-analyzing system configured to collect each of the mixed raw material before the burning and the clinker after the burning and to measure amounts of the fluorine, main components and free lime depending on the type collected.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract: Disclosed is a liquid processing jig for performing a predetermined processing on a workpiece using a processing liquid. The liquid processing jig includes: a liquid processing unit formed on a surface of the liquid processing jig and configured to perform a predetermined processing on the workpiece by the processing liquid; a liquid supplying unit configured to supply the processing liquid to the liquid processing unit; a liquid supplying channel configured to connect the liquid supplying unit and the liquid processing unit and supply the processing liquid from the liquid supplying unit to the liquid processing unit; and a liquid discharging channel configured to discharge the processing liquid from the liquid processing unit. The liquid supplying unit, the liquid supplying channel, the liquid processing unit, and the liquid discharging channel are provided to cause the processing liquid to flow by a capillary phenomenon.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.