Patents by Inventor Kazuo Saki
Kazuo Saki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180076311Abstract: A semiconductor device includes: a first nitride semiconductor layer, a second nitride semiconductor layer that is provided on the first nitride semiconductor layer and has a band gap larger than a band gap of the first nitride semiconductor layer, a gate electrode that is provided on the first nitride semiconductor layer, a first electrode that is electrically connected to the first nitride semiconductor layer, a second electrode disposed such that the gate electrode is positioned between the first electrode and the second electrode, and electrically connected to the first nitride semiconductor layer, and a first insulation layer that is provided between the gate electrode and the second electrode, disposed such that the second nitride semiconductor layer is positioned between the first nitride semiconductor layer and the first insulation layer, and including silicon oxide having an oxygen-to-silicon atomic ratio (O/Si) of 1.50 or more and 1.85 or less.Type: ApplicationFiled: February 24, 2017Publication date: March 15, 2018Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasunobu SAITO, Kohei OASA, Takuo KIKUCHI, Junji KATAOKA, Tatsuya SHIRAISHI, Akira YOSHIOKA, Kazuo SAKI
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Patent number: 9917182Abstract: A semiconductor device includes: a first nitride semiconductor layer, a second nitride semiconductor layer that is provided on the first nitride semiconductor layer and has a band gap larger than a band gap of the first nitride semiconductor layer, a gate electrode that is provided on the first nitride semiconductor layer, a first electrode that is electrically connected to the first nitride semiconductor layer, a second electrode disposed such that the gate electrode is positioned between the first electrode and the second electrode, and electrically connected to the first nitride semiconductor layer, and a first insulation layer that is provided between the gate electrode and the second electrode, disposed such that the second nitride semiconductor layer is positioned between the first nitride semiconductor layer and the first insulation layer, and including silicon oxide having an oxygen-to-silicon atomic ratio (O/Si) of 1.50 or more and 1.85 or less.Type: GrantFiled: February 24, 2017Date of Patent: March 13, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasunobu Saito, Kohei Oasa, Takuo Kikuchi, Junji Kataoka, Tatsuya Shiraishi, Akira Yoshioka, Kazuo Saki
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Patent number: 9852911Abstract: A semiconductor device includes a semiconductor layer, a first electrode located over the semiconductor layer and connected to the semiconductor layer, a second electrode spaced from the first electrode and located over the semiconductor layer and connected to the semiconductor layer, an insulation film located over the semiconductor layer, and a third electrode interposed between the first electrode and the second electrode, and location over a portion of the insulation film. The insulation film includes a first layer located on the semiconductor layer and between the first electrode and the second electrode and comprising silicon nitride, and a second layer located on the first layer and between the first electrode and the third electrode as well as between the second electrode and the third electrode, and comprising silicon nitride and an amount of oxygen larger than the first layer.Type: GrantFiled: August 20, 2015Date of Patent: December 26, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Kazuo Saki
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Publication number: 20160268389Abstract: A semiconductor device includes a semiconductor layer, a first electrode located over the semiconductor layer and connected to the semiconductor layer, a second electrode spaced from the first electrode and located over the semiconductor layer and connected to the semiconductor layer, an insulation film located over the semiconductor layer, and a third electrode interposed between the first electrode and the second electrode, and location over a portion of the insulation film. The insulation film includes a first layer located on the semiconductor layer and between the first electrode and the second electrode and comprising silicon nitride, and a second layer located on the first layer and between the first electrode and the third electrode as well as between the second electrode and the third electrode, and comprising silicon nitride and an amount of oxygen larger than the first layer.Type: ApplicationFiled: August 20, 2015Publication date: September 15, 2016Inventor: Kazuo SAKI
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Publication number: 20160079405Abstract: According to an embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, and a first insulating film. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer is provided over the first semiconductor layer, includes a nitride semiconductor, and contains composition different from the composition of the first semiconductor layer. The first insulating film is provided over the second semiconductor layer, covers at least a part of the first electrode, and contains silicon nitride. The hydrogen concentration in the first insulating film is greater than or equal to 5.0×1021 atoms/cm3 and less than or equal to 9.0×1021 atoms/cm3.Type: ApplicationFiled: February 19, 2015Publication date: March 17, 2016Inventor: Kazuo SAKI
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Patent number: 7700156Abstract: In a method of forming a silicon oxide film, a target substrate that has a silicon layer on a surface is loaded into a process area within a reaction container, while setting the process area to have a loading temperature of 400° C. or less. Then, the process area that accommodates the target substrate is heated, from the loading temperature to a process temperature of 650° C. or more. Water vapor is supplied into the reaction container during said heating the process area, while setting the water vapor to have a first concentration in an atmosphere of the process area, and setting the process area to have a first reduced pressure. After said heating the process area to the process temperature, an oxidation gas is supplied into the reaction container, thereby oxidizing the silicon layer to form a silicon oxide film.Type: GrantFiled: June 30, 2004Date of Patent: April 20, 2010Assignees: Tokyo Electron Limited, Kabushiki Kaisha ToshibaInventors: Kimiya Aoki, Katsushi Suzuki, Asami Shirakawa, Kenji Tago, Keisuke Suzuki, Kazuo Saki, Shinji Mori
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Publication number: 20100089316Abstract: A plasma treatment apparatus includes a susceptor, a silica cover covering a plasma generating area above the susceptor, a chamber housing the susceptor and the silica cover, a gas inlet introducing conditioning gas into the chamber, a plasma generator generating a plasma of the conditioning gas configured to perform conditioning of the silica cover, an analyzing unit configured to monitor changes in a nitride layer on the surface of the silica cover, and a control unit connected to the analyzing unit configured to determine completion of the conditioning based on the change in the nitride layer.Type: ApplicationFiled: December 7, 2009Publication date: April 15, 2010Inventor: Kazuo Saki
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Publication number: 20070026149Abstract: In a process of annealing an insulating film such as a silicon oxide film (SiO2) or a silicon oxynitride film (SiON) provided in a processing chamber 6 within an atmosphere of an inert gas 2 guided from a first mass flow controller 3 via a gas inlet 7, an amount of SiO sublimated from the surface of the insulating film in the processing chamber 6 is measured by a mass spectrometer 10, and an amount of oxygen gas 4 guided to the processing chamber 6 from a second mass flow controller 5 is controlled by a controller 1 so that the SiO concentration does not exceed a predetermined level, thereby effectively controlling the SiO sublimation. As a result, the film deterioration caused by the SiO sublimation is prevented and an insulating film having a high reliability and good characteristics can be formed in a controllable manner.Type: ApplicationFiled: July 28, 2006Publication date: February 1, 2007Inventors: Takashi Shimizu, Kazuo Saki, Kazuhiro Nishiki, Akihito Yamamoto, Shinji Mori
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Publication number: 20060269691Abstract: A plasma treatment apparatus includes a susceptor, a silica cover covering a plasma generating area above the susceptor, a chamber housing the susceptor and the silica cover, a gas inlet introducing conditioning gas into the chamber, a plasma generator generating a plasma of the conditioning gas configured to perform conditioning of the silica cover, an analyzing unit configured to monitor changes in a nitride layer on the surface of the silica cover, and a control unit connected to the analyzing unit configured to determine completion of the conditioning based on the change in the nitride layer.Type: ApplicationFiled: October 27, 2005Publication date: November 30, 2006Inventor: Kazuo Saki
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Publication number: 20060223334Abstract: A system for controlling lot processes, which are executed in parallel, includes: first and second processing tools processing wafers classified into the lots; a transfer tool transferring the wafers from the first to second processing tools; a recipe storage unit storing recipe data including first and second process periods; a determination module determining first abd second starting times so as to minimize a waiting interval between the first and second process periods, based on the recipe data; and a control module controlling the first and second processing tools by starting operations at the first and second starting times, respectively.Type: ApplicationFiled: March 27, 2006Publication date: October 5, 2006Inventor: Kazuo Saki
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Publication number: 20060217830Abstract: A semiconductor manufacturing apparatus includes a processing apparatus main body which executes a process related to manufacturing a semiconductor device, an internal apparatus controller which supplies a start signal to start a process and a stop signal to stop the process of the semiconductor device within the processing apparatus main body, and a process controller which calculates a physical characteristic of the semiconductor device currently being processed and sends the stop signal to the apparatus controller when a calculated value reaches a predetermined value.Type: ApplicationFiled: June 1, 2006Publication date: September 28, 2006Inventors: Kazuo Saki, Yukihiro Ushiku
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Patent number: 7082346Abstract: A semiconductor manufacturing apparatus which continuously executes oxidation and CVD in a multiprocess apparatus includes an internal apparatus controller which selects the type of process and supplies a start signal and stop signal for the process to the multiprocess apparatus, and a process controller which calculates the process state for each process on the basis of the internal information of the apparatus. Upon receiving the stop signal from the controller, the controller sends the stop signal to the multiprocess apparatus to stop the current process by the multiprocess apparatus and switches to the next process.Type: GrantFiled: June 10, 2003Date of Patent: July 25, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Kazuo Saki, Yukihiro Ushiku
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Publication number: 20050202686Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention comprises forming a semiconductor element on a semiconductor substrate, forming a silicon oxide film containing nitrogen on the semiconductor element and injecting heavy hydrogen into the silicon oxide film containing nitrogen.Type: ApplicationFiled: July 7, 2004Publication date: September 15, 2005Inventors: Kazuo Saki, Shinji Mori, Takashi Shimizu
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Publication number: 20050056220Abstract: In a method of forming a silicon oxide film, a target substrate that has a silicon layer on a surface is loaded into a process area within a reaction container, while setting the process area to have a loading temperature of 400° C. or less. Then, the process area that accommodates the target substrate is heated, from the loading temperature to a process temperature of 650° C. or more. Water vapor is supplied into the reaction container during said heating the process area, while setting the water vapor to have a first concentration in an atmosphere of the process area, and setting the process area to have a first reduced pressure. After said heating the process area to the process temperature, an oxidation gas is supplied into the reaction container, thereby oxidizing the silicon layer to form a silicon oxide film.Type: ApplicationFiled: June 30, 2004Publication date: March 17, 2005Inventors: Kimiya Aoki, Katsushi Suzuki, Asami Shirakawa, Kenji Tago, Keisuke Suzuki, Kazuo Saki, Shinji Mori
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Patent number: 6759314Abstract: A thermal nitride film is formed as a gate insulating film on a silicon substrate, and after a gate electrode material is formed on the insulating film, it is patterned to form gate electrodes. After processing the electrodes, part of the gate insulating film other than a portion thereof which lies under the gate electrodes is removed. Further, an insulating film (a post oxidation film) is formed on side walls and upper surfaces of the stacked gate structures and the exposed main surface of the silicon substrate by use of thermal oxidation method.Type: GrantFiled: September 26, 2000Date of Patent: July 6, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Wakako Moriyama, Naoki Kai, Hiroaki Hazama, Keiki Nagai, Yuji Fukazawa, Kazuo Saki, Yoshio Ozawa, Yasumasa Suizu
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Publication number: 20040044419Abstract: A semiconductor manufacturing apparatus which continuously executes oxidation and CVD in a multiprocess apparatus includes an internal apparatus controller which selects the type of process and supplies a start signal and stop signal for the process to the multiprocess apparatus, and a process controller which calculates the process state for each process on the basis of the internal information of the apparatus. Upon receiving the stop signal from the controller, the controller sends the stop signal to the multiprocess apparatus to stop the current process by the multiprocess apparatus and switches to the next process.Type: ApplicationFiled: June 10, 2003Publication date: March 4, 2004Inventors: Kazuo Saki, Yukihiro Ushiku
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Publication number: 20010034107Abstract: An element isolation method of a semiconductor device comprises the steps of forming an oxide film on a semiconductor substrate; forming a nitride film on the oxide film; forming an isolation trench on the semiconductor device, the isolation trench being formed through the nitride film and oxide film; forming an oxide insulation layer on the semiconductor substrate to fill the isolation trench and cover the nitride film; flattening the surface of the semiconductor substrate to expose the nitride film by removing a surface portion of the oxide insulation layer in the isolation trench and the oxide insulation layer on the nitride film; heating the flattened semiconductor substrate in a nitrogen-containing gas atmosphere under reduced pressure to form an oxy-nitride film at an interface between an inside wall of the isolation trench and the oxide insulation layer in the isolation trench; and removing the nitride film and the oxide film on the semiconductor substrate.Type: ApplicationFiled: April 25, 2001Publication date: October 25, 2001Applicant: Kabushiki Kaisha ToshibaInventors: Yuji Fukazawa, Kazuo Saki
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Patent number: 6291300Abstract: An element isolation method of a semiconductor device comprises the steps of forming an oxide film on a semiconductor substrate; forming a nitride film on the oxide film; forming an isolation trench on the semiconductor device, the isolation trench being formed through the nitride film and oxide film; forming an oxide insulation layer on the semiconductor substrate to fill the isolation trench and cover the nitride film; flattening the surface of the semiconductor substrate to expose the nitride film by removing a surface portion of the oxide insulation layer in the isolation trench and the oxide insulation layer on the nitride film; heating the flattened semiconductor substrate in a nitrogen-containing gas atmosphere under reduced pressure to form an oxy-nitride film at an interface between an inside wall of the isolation trench and the oxide insulation layer in the isolation trench; and removing the nitride film and the oxide film on the semiconductor substrate.Type: GrantFiled: September 13, 2000Date of Patent: September 18, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Yuji Fukazawa, Kazuo Saki
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Publication number: 20010015174Abstract: semiconductor device, including the step of supplying an oxidizing gas and a nitriding gas onto one main surface of a semiconductor substrate while heating the substrate so as to oxynitride the surface region of the substrate, wherein the supplying step is performed such that the gaseous phase above the main surface of the substrate forms a first region having a substantially uniform temperature in a direction perpendicular to the main surface of the substrate and a second region interposed between the first region and the substrate and having a temperature gradient in a direction perpendicular to the main surface of the substrate such that the temperature is elevated toward the substrate, and the distance from the main surface of the substrate to the interface between the first and second regions is set at 9.5 cm or less.Type: ApplicationFiled: May 7, 2001Publication date: August 23, 2001Applicant: Kabushiki Kaisha ToshibaInventors: Kazuo Saki, Shuji Katsui
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Patent number: 6251801Abstract: Disclosed is a method of manufacturing a semiconductor device, including the step of supplying an oxidizing gas and a nitriding gas onto one main surface of a semiconductor substrate while heating the substrate so as to oxynitride the surface region of the substrate, wherein the supplying step is performed such that the gaseous phase above the main surface of the substrate forms a first region having a substantially uniform temperature in a direction perpendicular to the main surface of the substrate and a second region interposed between the first region and the substrate and having a temperature gradient in a direction perpendicular to the main surface of the substrate such that the temperature is elevated toward the substrate, and the distance from the main surface of the substrate to the interface between the first and second regions is set at 9.5 cm or less.Type: GrantFiled: October 6, 1999Date of Patent: June 26, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Kazuo Saki, Shuji Katsui