Patents by Inventor Kazuo Taki

Kazuo Taki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120305899
    Abstract: An object of the present invention is to provide a polymer compound providing high charge mobility. The polymer compound of the present invention has a repeating unit represented by the formula (1): wherein Ar1 and Ar2 are each an aromatic hydrocarbon ring, a heterocycle, or a fused ring of an aromatic hydrocarbon ring and a heterocycle; and R1, R2, R3 and R4 each represent a hydrogen atom, an alkyl group, an alkoxy group, an alkylthio group, an aryl group, an aryloxy group, an arylthio group, an arylalkyl group, an arylalkoxy group, an arylalkylthio group, a substituted silyl group, an unsubstituted or substituted carboxyl group, a monovalent heterocyclic group, a cyano group or a fluorine atom.
    Type: Application
    Filed: December 22, 2010
    Publication date: December 6, 2012
    Applicants: NATIONAL UNIVERSITY OF CORPORATION HIROSHIMA UNIVERSITY, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Kazuo Taki, Itaru Osaka, Kenji Kohiro, Kenichiro Ohya, Kunihito Miyake
  • Patent number: 6509761
    Abstract: Very high speed operation and reduction of power consumption are realized simultaneously in a two-wire type logical circuit having a halt value and an effective value as signal values. Signal rise transition delay time and signal fall transition delay time are purposely designed asymmetrically and an effective value propagation delay is shortened, thereby accelerating an operating speed of the logical circuit. By eliminating a clock signal from a DOMINO circuit, power consumption is reduced. An architecture for concealing a halt value propagation delay is employed.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: January 21, 2003
    Assignee: A-I-L Corporation
    Inventor: Kazuo Taki
  • Publication number: 20020101262
    Abstract: Very high speed operation and reduction of power consumption are realized simultaneously in a two-wire type logical circuit having a halt value and an effective value as signal values. Signal rise transition delay time and signal fall transition delay time are purposely designed asymmetrically and an effective value propagation delay is shortened, thereby accelerating an operating speed of the logical circuit. By eliminating a clock signal from a DOMINO circuit, power consumption is reduced. An architecture for concealing a halt value propagation delay is employed.
    Type: Application
    Filed: November 13, 2001
    Publication date: August 1, 2002
    Applicant: A-I-L CORPORATION
    Inventor: Kazuo Taki
  • Publication number: 20020000833
    Abstract: To provide a small-area and low-power-consuming logic gate cell which is constructed of a circuit of two inverting logic gates connected in series in a layout of four-step diffusion regions. A first inverting logic gate is formed of a small transistor on internal two-step diffusion regions, a second inverting logic gate is formed of external two-step diffusion regions, and output wirings of the second inverting logic gate is formed of second metal layer wirings so that the second metal layer wirings extend over the first inverting logic gate.
    Type: Application
    Filed: June 15, 1999
    Publication date: January 3, 2002
    Inventor: KAZUO TAKI
  • Patent number: 6329845
    Abstract: To provide a small-area and low-power-consuming logic gate cell which is constructed of a circuit of two inverting logic gates connected in series in a layout of four-step diffusion regions. A first inverting logic gate is formed of a small transistor on internal two-step diffusion regions, a second inverting logic gate is formed of external two-step diffusion regions, and output wirings of the second inverting logic gate is formed of second metal layer wirings so that the second metal layer wirings extend over the first inverting logic gate.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: December 11, 2001
    Assignee: AIL Co., Ltd.
    Inventor: Kazuo Taki
  • Patent number: 6005418
    Abstract: Disclosed is a low power consuming logic circuit to restrain a short circuit current which flows within an inverter circuit of an inverter having a clock input connected behind a pass-transistor logic circuit. In the logic circuit, the inverter having a clock input is provided on the output of a pass-transistor logic circuit. The inverter having a clock input includes the inverter circuit and write control means. A data holding circuit is connected to the output of the write control means. In the logic circuit, a clock is input to the inverter having a clock input after the output of the pass-transistor logic circuit is stabilized. Thus, the short circuit current which flows in the inverter circuit is restrained. In addition to the logic circuit, a positive feedback circuit for supplying an inverted signal from the inverter circuit to the output of the inverter having a clock input can be provided.
    Type: Grant
    Filed: December 11, 1996
    Date of Patent: December 21, 1999
    Assignee: Yugen Kaisha A.I.L.
    Inventor: Kazuo Taki
  • Patent number: 4397951
    Abstract: An elastase-containing composition containing 0.5 to 50 parts by weight of sucrose fatty acid ester per part by weight of pure elastase, which composition permits elastase, useful as medicine for arterioscloerosis and hyperlipemia, to be absorbed in increased amount through intenstine.
    Type: Grant
    Filed: January 27, 1982
    Date of Patent: August 9, 1983
    Assignee: Eisai Co., Ltd.
    Inventors: Kazuo Taki, Ryoichi Machida, Kouichi Katayama
  • Patent number: 4325942
    Abstract: A novel ubidecarenone composition comprising ubidecarenone and higher fatty acid(s) or monoglyceride(s) of higher fatty acid(s), or a mixture thereof, which has improved absorptivity through the lymphatic duct.
    Type: Grant
    Filed: July 15, 1980
    Date of Patent: April 20, 1982
    Assignee: Eisai Co., Ltd.
    Inventors: Kazuo Taki, Hideo Takahira