Abstract: A semiconductor device includes: a nonvolatile memory cell including first memory cells and second memory cells; a bit latch; and a saved register. In a first writing operation, first writing data are stored in the bit latch and the saved register, and writing to the first memory cells is executed based on the first writing data. During the first writing operation, the first writing operation is interrupted based on a suspension command, and a second writing operation is executed. In the second writing operation, second writing data are stored in the bit latch, and writing to the second memory cells is executed based on the second writing data. After the second writing operation is ended, the first writing data is reset to the bit latch based on a resume command, and the interrupted first writing operation is restarted based on the first writing data reset to the bit latch.

Abstract: A semiconductor device includes: a nonvolatile memory cell including first memory cells and second memory cells; a bit latch; and a saved register. In a first writing operation, first writing data are stored in the bit latch and the saved register, and writing to the first memory cells is executed based on the first writing data. During the first writing operation, the first writing operation is interrupted based on a suspension command, and a second writing operation is executed. In the second writing operation, second writing data are stored in the bit latch, and writing to the second memory cells is executed based on the second writing data. After the second writing operation is ended, the first writing data is reset to the bit latch based on a resume command, and the interrupted first writing operation is restarted based on the first writing data reset to the bit latch.

Abstract: An object of the present invention is to increase a writing speed to a flash memory while suppressing an increase in noise. In the high-speed write mode, the memory controller simultaneously performs a first write operation with a second write current having a current value smaller than the first write current with respect to a second number of memory cells having a larger number than the first write current. At the completion of the first write operation, the memory controller simultaneously performs the second write operation by the third write current having a larger current value than the second write current with respect to the memory cell determined by the sense amplifier to have not completed the write operation in the determination process.

Abstract: An object of the present invention is to increase a writing speed to a flash memory while suppressing an increase in noise. In the high-speed write mode, the memory controller simultaneously performs a first write operation with a second write current having a current value smaller than the first write current with respect to a second number of memory cells having a larger number than the first write current. At the completion of the first write operation, the memory controller simultaneously performs the second write operation by the third write current having a larger current value than the second write current with respect to the memory cell determined by the sense amplifier to have not completed the write operation in the determination process.

Abstract: In an internal power supply voltage control apparatus, reference voltage generating circuit generates a reference voltage. A first internal power supply reference voltage generating circuit generates a first internal power supply reference voltage in accordance with the reference voltage, and a second internal power supply reference voltage generating circuit generates a second internal power supply reference voltage in accordance with a voltage applied to a predetermined pad. A test mode selecting circuit activates one of the first and second internal power supply reference voltage generating circuits in accordance with a control signal. An internal power supply voltage generating circuit generates an internal power supply voltage in accordance with one of the first and second internal power supply reference voltages generated from an activated one of the first and second internal power supply reference voltage generating circuits.

Abstract: In an internal power supply voltage control apparatus, reference voltage generating circuit generates a reference voltage. A first internal power supply reference voltage generating circuit generates a first internal power supply reference voltage in accordance with the reference voltage, and a second internal power supply reference voltage generating circuit generates a second internal power supply reference voltage in accordance with a voltage applied to a predetermined pad. A test mode selecting circuit activates one of the first and second internal power supply reference voltage generating circuits in accordance with a control signal. An internal power supply voltage generating circuit generates an internal power supply voltage in accordance with one of the first and second internal power supply reference voltages generated from an activated one of the first and second internal power supply reference voltage generating circuits.

Abstract: A decoder circuit quickly switches an output signal thereof. The decoder circuit, which decodes a plurality of input address signals to output a decoded signal on an output terminal, comprises a switch circuit that receives the address signals and connects a node to a ground line or cuts off the node from the ground line according to the plurality of address signals and a p-channel transistor providing a power supply voltage for the node, a gate electrode of the p-channel transistor connecting with a ground line when the node connects with the ground line and receiving a voltage having a predetermined level intermediate a level of the power supply voltage and a level of the ground line, when the node is cut off from the ground line, wherein the decoded signal changes according to a voltage level of the node.