Patents by Inventor Kazushi Komeda

Kazushi Komeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230363165
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and composite layers, each of the composite layers includes a plurality of electrically conductive word line strips and a plurality of dielectric isolation structures, and each of the insulating layers has an areal overlap with each electrically conductive word line strip and each dielectric isolation structure within the composite layers within a memory array region in a plan view along a vertical direction, rows of memory openings arranged along the first horizontal direction, where each row of memory openings of the rows of memory openings vertically extends through each insulating layer within the alternating stack and one electrically conductive strip for each of the composite layers, and rows of memory opening fill structures located within the rows of memory openings, where each of the memory opening fill structures includes a vertical stack of memory elements and a vertical semiconductor channel.
    Type: Application
    Filed: July 6, 2023
    Publication date: November 9, 2023
    Inventors: Takaaki IWAI, Kazushi KOMEDA, Zhen CHEN
  • Patent number: 10096654
    Abstract: An alternating material stack of insulator lines and first electrically conductive material layers is formed over a substrate, and is patterned to provide alternating stacks of insulating layers and first electrically conductive lines. A metal can be selectively deposited on the physically exposed sidewalls of the first electrically conductive material layers to form metal lines, while not growing from the surfaces of the insulator lines. The metal lines are oxidized to form metal oxide lines that are self-aligned to the sidewalls of the first electrically conductive lines. Vertically extending second electrically conductive lines can be formed as a two-dimensional array of generally pillar-shaped structures between the alternating stacks of the insulator lines and the first electrically conductive lines. Each portion of the metal oxide lines at junctions of first and second electrically conductive lines constitute a resistive memory element for a resistive random access memory (ReRAM) device.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: October 9, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shin Kikuchi, Kazushi Komeda, Takuya Futase, Teruyuki Mine, Seje Takaki, Eiji Hayashi, Toshihide Tobitsuka
  • Publication number: 20170077184
    Abstract: An alternating material stack of insulator lines and first electrically conductive material layers is formed over a substrate, and is patterned to provide alternating stacks of insulating layers and first electrically conductive lines. A metal can be selectively deposited on the physically exposed sidewalls of the first electrically conductive material layers to form metal lines, while not growing from the surfaces of the insulator lines. The metal lines are oxidized to form metal oxide lines that are self-aligned to the sidewalls of the first electrically conductive lines. Vertically extending second electrically conductive lines can be formed as a two-dimensional array of generally pillar-shaped structures between the alternating stacks of the insulator lines and the first electrically conductive lines. Each portion of the metal oxide lines at junctions of first and second electrically conductive lines constitute a resistive memory element for a resistive random access memory (ReRAM) device.
    Type: Application
    Filed: September 11, 2015
    Publication date: March 16, 2017
    Inventors: Shin KIKUCHI, Kazushi KOMEDA, Takuya FUTASE, Teruyuki MINE, Seje TAKAKI, Eiji HAYASHI, Toshihide TOBITSUKA
  • Publication number: 20110042733
    Abstract: A semiconductor device includes a plurality of first electrodes standing over a substrate, and a supporter that supports the plurality of first electrodes in standing. The supporter includes a stack of first and second supporting films. The first supporting film has a compressive stress. The second supporting film has a tensile stress.
    Type: Application
    Filed: August 17, 2010
    Publication date: February 24, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Kazushi Komeda, Takashi Miyajima, Shigeru Sugioka, Takashi Miyamura
  • Publication number: 20100176486
    Abstract: A semiconductor device includes a memory cell region and a peripheral circuit region. The memory cell region includes a first region and a second region surrounding the first region. The first region includes a plurality of first electrodes, a plurality of first support portions, and a second support portion. The plurality of first electrodes upwardly extends. The plurality of first support portions upwardly extends along the plurality of first electrodes. Each of the plurality of first support portions mechanically supports corresponding one of the plurality of first electrodes. The second support portion contacts with the plurality of the first support portions. The second support portion connects between each of the plurality of first electrodes.
    Type: Application
    Filed: January 8, 2010
    Publication date: July 15, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Takashi Miyajima, Shigeru Sugioka, Kazushi Komeda, Takashi Miyamura, Kohei Inoue