Patents by Inventor Kazushige Itazu

Kazushige Itazu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus to optimize power wiring layout and generate wiring layout data for a semiconductor integrated circuit
    Patent number: 6405354
    Abstract: A program for generating layout data for a semiconductor integrated circuit analyzes a power network of individual modules in order to determine when an iterative layout process is complete. First, the individual modules are laid out and power supply wirings to the modules are laid out. Next, using cell size information about the cells within each of the modules, the cells of each module are temporarily arranged within the modules. Then, the power wirings and power supply terminals for each module are specified. A power network of each module is then sampled based on the cells, power wirings and power supply terminals of each module. Using the sample data, it is determined whether the modules and the power supply wirings to the modules need to be laid out again. The program may be executed on a CAD system.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: June 11, 2002
    Assignee: Fujitsu Limited
    Inventors: Kazushige Itazu, Takayuki Matsuzawa, Takanori Nawa
  • Manufacturing method and apparatus of a semiconductor integrated circuit device
    Patent number: 6035111
    Abstract: According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: March 7, 2000
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Rieko Suzuki, Kiyoshi Saida, Kazushige Itazu, Eiji Fujine, Yoshihiro Kamiya, Yoshitaka Uchida, Takako Murakami, Teruhisa Tsuyuki, Kazunori Kawazoe, Takeshi Shimazaki, Yukimi Nishiwaki
  • Manufacturing method and apparatus of a semiconductor integrated circuit device
    Patent number: 5618744
    Abstract: According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.
    Type: Grant
    Filed: September 22, 1993
    Date of Patent: April 8, 1997
    Assignees: Fujitsu Ltd., Fujitsu VLSI Ltd.
    Inventors: Rieko Suzuki, Kiyoshi Saida, Kazushige Itazu, Eiji Fujine, Yoshihiro Kamiya, Yoshitaka Uchida, Takako Murakami, Teruhisa Tsuyuki, Kazunori Kawazoe, Takeshi Shimazaki, Yukimi Nishiwaki