Patents by Inventor Kazutaka KAMIJO

Kazutaka KAMIJO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11887845
    Abstract: A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: January 30, 2024
    Assignees: GLOBALWAFERS JAPAN CO., LTD., TOHOKU UNIVERSITY
    Inventors: Kazutaka Kamijo, Etsuo Fukuda, Takashi Ishikawa, Koji Izunome, Moriya Miyashita, Takao Sakamoto, Tetsuo Endoh
  • Publication number: 20220093396
    Abstract: A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.
    Type: Application
    Filed: September 29, 2021
    Publication date: March 24, 2022
    Applicants: GLOBALWAFERS JAPAN CO., LTD., TOHOKU UNIVERSITY
    Inventors: Kazutaka KAMIJO, Etsuo FUKUDA, Takashi ISHIKAWA, Koji IZUNOME, Moriya MIYASHITA, Takao SAKAMOTO, Tetsuo ENDOH
  • Publication number: 20200211840
    Abstract: A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.
    Type: Application
    Filed: July 17, 2018
    Publication date: July 2, 2020
    Applicants: GlobalWafers Japan Co., Ltd., TOHOKU UNIVERSITY
    Inventors: Kazutaka KAMIJO, Etsuo FUKUDA, Takashi ISHIKAWA, Koji IZUNOME, Moriya MIYASHITA, Takao SAKAMOTO, Tetsuo ENDOH