Abstract: A semiconductor memory device includes a plurality of memory cells each specified by selecting one of rows and one of columns, a plurality of word lines to each of which the memory cells associated with selected one of the rows are connected in a branch form, for selecting the rows, and a plurality of bit lines to each of which the memory cells associated with selected one of the columns are connected in a branch form, for selecting the columns and providing data transmission paths for the memory cells, wherein at least one wiring of the word lines and bit lines constitutes part of at least one closed circuit. Thus, even if breaking of wire occurs in part of the wiring in the manufacturing process or in use, the memory device can be prevented from becoming a defective product due to the breaking of wire. As a result, high manufacturing yield and high reliability in use can be obtained.

Abstract: A semiconductor memory device having a plurality of memory cells, each memory cell having two nodes, an electric potential of each node designates a stored data, comprises: a word line; a pair of bit lines; a pair of field effect transistors (FETs) connected between the word line and the nodes; a pair of diodes connected between the bit lines and the nodes; a pair of load means connected between the nodes and a first potential; and an inverter connected to the word line for driving the FETs, wherein the electrical potential of the nodes are read out by the change of the potential of the word line controlled by the inverter.

Abstract: A semiconductor integrated circuit comprises a plurality of memory blocks each provided with a set of word lines shared by the other memory blocks so that the memory blocks may be accessed separately by using different address signals entered on a time division basis. The integrated circuit also comprises one or more than one decoders for choosing a word line from an end to allow access to any of the plurality of memory blocks and a word line latch circuit inserted into the set of word lines between a pair of memory blocks. With such an arrangement, the number of decoders, word lines, bit lines, memory cells and sense amplifiers as well as the overall size of the integrated circuit can be minimized. Besides, the access time to a certain memory block that constitutes a critical factor to determine the performance the entire integrated circuit can be curtailed so that it may be accessed in a very short period of time and consequently the performance of the circuit may be remarkably improved.

Abstract: A field-effect transistor device comprising a p-type silicon substrate, a pair of n-channel MOS transistors, and a wiring means connecting the MOS transistors. The first MOS transistor has a gate electrode provided above the substrate and extending in one direction, and two regions formed in the substrate, located on two opposing sides of the gate electrode, and serving as a source and a drain. The second MIS transistor has a gate electrode provided above the substrate and extending in said one direction, and two regions formed in the substrate, located on two opposing sides of this gate electrode, and serving as a source and a drain. The wiring means includes bit lines BL and BL which permit the source-drain paths of the first and second MIS transistors to be oriented in the same direction.

Abstract: This invention is directed to a device to decode a row address by a row decoder thereafter to latch the decoded signal by a latch circuit, thus allowing the latched signal to drive a memory cell in a memory cell array. Since respective addresses are latched after decoded as stated above, no decode time is included in one cycle time and the cycle time is therefore shortened.

Abstract: A dynamic read/write memory in which refreshing is performed within a read/write cycle so that write recovery time is not prolonged. A word line corresponding to a current address is continuously rendered operative within a write period. When a write operation is completed, the word line is rendered operative so that refreshing is initiated. A word line is rendered operative only within a given period of a read period.

Abstract: A sense circuit includes first and second input nodes, first and second output nodes, first to fifth MOSFETs of N-channel type, and first and second potential setting circuits, and the first and second output nodes are precharged to a power source potential by the first and second potential setting circuits before the sensing operation is started. After this, the first MOSFET is turned on by a control signal to start the sensing operation. After the sensing operation is started, the potentials of the first and second input nodes are respectively amplified by the second and third MOSFETs and the fourth and fifth MOSFETs and the amplified potentials are derived from the first and second output nodes.

Abstract: A virtual type static semiconductor memory device according to the present invention comprises a refresh detector circuit for detecting the enabling operation of a refresh control circuit and a terminal for outputting to an outside a detection signal which is generated from the refresh detector circuit. The virtual type static semiconductor memory device informs a present refresh operation to the outside when it is accessed from the outside during the time period in which a refresh operation is conducted in the semiconductor memory device. A system employing the semiconductor memory device allows a slow access at that time only and allows access to be gained to the semiconductor memory device at high speed at other times.

Abstract: A semiconductor memory device includes a memory cell array, a spare memory cell array, a first addressing circuit for designating an address of the memory cell array, a second addressing circuit for designating an address of the spare memory cell array, a drive circuit for activating a select line designated by each of the first and second addressing circuits, a program circuit for generating a predetermined output based on whether the memory cell array has a defect or fault or not, and a select circuit responsive to an output from the program circuit for supplying an activation signal to the designated select line at an earlier timing when there is no fault in the memory array cell, and supplying an activation signal delayed by a time necessary for the selection of the spare memory cell array when there is a fault in the memory cell array.

Abstract: A semiconductor integrated circuit comprises a pair of P-channel and N-channel MOS output transistors connected in series between a power source voltage node and a ground node, a first logic circuit for controlling a gate potential of the P-channel MOS output transistor, a first current control circuit for controlling a current flowing into a ground potential path of the first logic circuit, a second logic circuit for controlling a gate potential of the N-channel MOS output transistor, a second current control circuit for controlling a current flowing into a power source potential path of the second logic circuit, and the first and second current control circuits having a current-temperature characteristic and a current-power source voltage characteristic which are inversely proportional to those of the MOS output transistors.

Abstract: A random access memory having blocks of memory cells arranged two-dimensionally in groups associated with pairs of data lines. Each pair of data lines transfers write-data to and read-data from respective groups of memory blocks. A column decoder selects, for a plurality of groups, one memory block from among the blocks in a group to be connected to a corresponding data line in accordance with a column address signal. A section decoder connects the coresponding data lines which were connected to selected ones of the memory blocks to a data input/output circuit.

Abstract: The invention discloses a semiconductor memory device possessing high operational reliability. In the semiconductor memory device according to the invention, a plurality of well regions of a conductivity type different from that of a semiconductor substrate are formed in the semiconductor substrate, and a memory cell array and a bit line driver are formed in other well regions, situated away from each other. With this arrangement, the number of signal lines to be connected to the well region in which the memory cell array is formed can be reduced, and the adverse influence of minority carriers generated upon operation of the bit line driver can be prevented. With this arrangement, well bias can be applied only to memory cell array. As a result, the operational reliability of the semiconductor memory device can be improved.

Abstract: Two or more voltage bootstrap circuits are included, and are sequentially operated. A continuous data write/read operation can be performed at a high speed. One of the two voltage bootstrap circuits is used for the data write/read operation and the other thereof is used for the refresh operation, thereby shortening the time required for refreshing.

Abstract: This invention provides a refresh operation control circuit for a semiconductor memory device. Two flip-flop circuits respectively temporarily hold a normal read start command signal and a refresh start command signal generated within the memory device. A normal operation/refresh operation priority determining circuit wherein 2-input logic circuits are cross-connected so that one output in each case of each of these two flip-flop circuits provides one input of the other flip-flop circuit. The priority determining circuit determines the priority of normal read operation and refresh operation in accordance with the logic level relationship of the one inputs. Either control of the start of normal read operation or control of the start of refresh operation is carried out in accordance with the output of this determination.