Patents by Inventor Kazutaka Taniguchi
Kazutaka Taniguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929781Abstract: An objective is to provide a terminal device, a communication method, and a communication system in which the time taken by connection operations/authentication operations does not increase proportionally with the pattern length, even if the transmitting side and the receiving side are not synchronized. A terminal device, a communication method, and a communication system according to the present invention create n pieces of signal information (n-bit patterns) by sequentially shifting each bit of a single piece of received signal information (n-bit pattern) one bit at a time. Through the above, signal information time-shifted by one bit each is obtained. Thus, even if the transmitting side and the receiving side are not synchronized, one of the n pieces of signal information is a signal synchronized with the transmitting side. Thereafter, the signal synchronized with the transmitting side can be detected by a brute-force calculation with the patterns (ID information) in the list.Type: GrantFiled: January 23, 2020Date of Patent: March 12, 2024Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Ryota Shiina, Tomohiro Taniguchi, Kazutaka Hara, Shinya Tamaki, Tomoki Murakami, Toshiro Nakahira
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Patent number: 11055206Abstract: A non-transitory computer-readable storage medium storing a program that causes a computer to execute a process, the process including executing one of a plurality of programs, acquiring a status of variation in an internal state of a memory occurred in response to the executing, determining whether a specified status pattern is stored in a storage device that stores a plurality of status patterns of variation in an internal state of the memory, the specified status pattern satisfying a predetermined criterion regarding a similarity with the acquired status, when the specified status pattern is stored in the storage device, generating a test scenario that is a combination of programs including the executed program, and when the specified status pattern is not stored in the storage device, suppressing the generating the test scenario.Type: GrantFiled: October 2, 2018Date of Patent: July 6, 2021Assignee: FUJITSU LIMITEDInventors: Yuichiroh Takoh, Atsushi Kaneko, Seiya Shindo, Eiji Mizunuma, Hisaya Fujii, Yasuhiro Suzuki, Kazutaka Taniguchi
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Patent number: 11010633Abstract: A technology capable of effectively and stably correcting brightness unevenness in an image obtained by imaging is provided. An image processing method includes an image obtaining step of obtaining an original image obtained by imaging an imaging object together with a substantially uniform background, an approximation step of specifying an approximation formula for approximating a two-dimensional luminance profile of the original image to a probability density function of a two-dimensional normal distribution, and a correction step of correcting a luminance value of each pixel constituting the original image on the basis of a luminance value of the two-dimensional luminance profile expressed by the approximation formula.Type: GrantFiled: October 13, 2016Date of Patent: May 18, 2021Assignee: SCREEN HOLDINGS CO., LTD.Inventors: Hiroki Fujimoto, Kazutaka Taniguchi
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Publication number: 20190102283Abstract: A non-transitory computer-readable storage medium storing a program that causes a computer to execute a process, the process including executing one of a plurality of programs, acquiring a status of variation in an internal state of a memory occurred in response to the executing, determining whether a specified status pattern is stored in a storage device that stores a plurality of status patterns of variation in an internal state of the memory, the specified status pattern satisfying a predetermined criterion regarding a similarity with the acquired status, when the specified status pattern is stored in the storage device, generating a test scenario that is a combination of programs including the executed program, and when the specified status pattern is not stored in the storage device, suppressing the generating the test scenario.Type: ApplicationFiled: October 2, 2018Publication date: April 4, 2019Applicant: FUJITSU LIMITEDInventors: Yuichiroh Takoh, ATSUSHI KANEKO, Seiya Shindo, Eiji Mizunuma, Hisaya Fujii, Yasuhiro Suzuki, Kazutaka Taniguchi
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Publication number: 20180307938Abstract: A technology capable of effectively and stably correcting brightness unevenness in an image obtained by imaging is provided. An image processing method includes an image obtaining step of obtaining an original image obtained by imaging an imaging object together with a substantially uniform background, an approximation step of specifying an approximation formula for approximating a two-dimensional luminance profile of the original image to a probability density function of a two-dimensional normal distribution, and a correction step of correcting a luminance value of each pixel constituting the original image on the basis of a luminance value of the two-dimensional luminance profile expressed by the approximation formula.Type: ApplicationFiled: October 13, 2016Publication date: October 25, 2018Applicant: SCREEN HOLDINGS CO., LTD.Inventors: Hiroki FUJIMOTO, Kazutaka TANIGUCHI
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Publication number: 20180024904Abstract: A test support device includes a processor configured to acquire event information on events which occur during an execution of a target program. The processor is configured to classify the events into event groups on basis of similarity of timings at which the respective events occur. The processor is configured to calculate, for each of the event groups, a summed value of evaluation values of the respective events classified into the relevant event group. The processor is configured to determine for each of the event groups, on basis of the summed value, whether a breakpoint of a target process executed by the target program is present at a timing corresponding to the relevant event group. The processor is configured to display timing information indicating a timing at which a breakpoint is determined to be present, in association with elapsed time after a start of executing the target program.Type: ApplicationFiled: June 21, 2017Publication date: January 25, 2018Applicant: FUJITSU LIMITEDInventors: Hideki Gou, Atsushi Kaneko, Seiya Shindo, Eiji Mizunuma, Kazutaka Taniguchi, Yasuhiro Suzuki
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Patent number: 9659607Abstract: To improve reading accuracy of a sense amplifier circuit and a semiconductor memory device. A sense amplifier circuit includes an N type FET which is a sensing transistor connected between a power supply and a ground via a data line that extends to a memory cell, a resistance element that is connected between a gate of the sensing transistor and the power supply, and a capacitance element that is connected between the gate of the sensing transistor and the ground.Type: GrantFiled: July 29, 2015Date of Patent: May 23, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hidetoshi Ozoe, Yasuhiro Tonda, Kazutaka Taniguchi
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Patent number: 9327488Abstract: A carrier and a substrate are aligned even if an imager cannot be simultaneously focused on alignment marks formed on both the carrier and the substrate. Center of gravity positions G1m of an alignment pattern element AP1 on a substrate and G2m of an alignment pattern element AP2 on a transparent blanket are calculated by image processing from an image IM imaged via the blanket by a CCD camera. The position of the center of gravity Gm2 is specified by a process associated with edge extraction from the image imaged with the alignment pattern element AP2 on the blanket being in focus. High spatial frequency components are removed and low frequency components are extracted for the alignment pattern element AP1 on the substrate imaged out of focus to have a blurred outline, and the position of the center of gravity G1m is specified from an extraction result.Type: GrantFiled: August 30, 2012Date of Patent: May 3, 2016Assignee: SCREEN Holdings Co., Ltd.Inventors: Kazutaka Taniguchi, Masafumi Kawagoe, Mikio Masuichi, Tomoyuki Komura
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Publication number: 20150332741Abstract: To improve reading accuracy of a sense amplifier circuit and a semiconductor memory device. A sense amplifier circuit includes an N type FET which is a sensing transistor connected between a power supply and a ground via a data line that extends to a memory cell, a resistance element that is connected between a gate of the sensing transistor and the power supply, and a capacitance element that is connected between the gate of the sensing transistor and the ground.Type: ApplicationFiled: July 29, 2015Publication date: November 19, 2015Inventors: Hidetoshi OZOE, Yasuhiro TONDA, Kazutaka TANIGUCHI
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Patent number: 9117494Abstract: To improve reading accuracy of a sense amplifier circuit and a semiconductor memory device. A sense amplifier circuit includes an N type FET which is a sensing transistor connected between a power supply and a ground via a data line that extends to a memory cell, a resistance element that is connected between a gate of the sensing transistor and the power supply, and a capacitance element that is connected between the gate of the sensing transistor and the ground.Type: GrantFiled: February 22, 2013Date of Patent: August 25, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hidetoshi Ozoe, Yasuhiro Tonda, Kazutaka Taniguchi
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Patent number: 9064922Abstract: A substrate inspection apparatus for detecting a condition of an EBR line at a substrate edge, comprising a turntable for rotating a substrate having a film coated thereon, a light irradiator and a photoelectric converter that receives specularly reflected light from the substrate and outputs a captured image signal. A two-dimensional image is generated by adding detection values of electrical signals corresponding to one radial scan from a center of the substrate for one turn of a rotator, and a changing point is judged using a judgment band set along one direction of the two-dimensional image.Type: GrantFiled: January 6, 2012Date of Patent: June 23, 2015Assignee: SCREEN Holdings Co., Ltd.Inventors: Taigo Nakajima, Kunio Ueta, Kazutaka Taniguchi
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Patent number: 9041907Abstract: A drawing device draws a pattern on a substrate by radiating light from an optical head part on a target object (for example, substrate) which relatively moves with respect to the optical head part. Here, the optical head part has a spatial modulating unit which spatially modulates light from a light source, based on pattern data, and an optical path corrector which shifts the route of light spatially modulated in the spatial modulating unit at precision subdivided more than units of spatial modulation in the spatial modulating unit (more specifically, for example, units of pixels of spatial light modulator).Type: GrantFiled: April 14, 2011Date of Patent: May 26, 2015Assignee: SCREEN HOLDINGS CO., LTD.Inventors: Yoshiyuki Nakazawa, Yoshio Furuya, Ryosuke Ito, Kenji Nakanishi, Kazutaka Taniguchi, Ryo Yamada
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Publication number: 20140209250Abstract: In a detaching apparatus, a detachment starter bends one end part of a first plate-like body into a cylindrical or prismatic surface in a direction opposite to a second plate-like body, thereby forming a single and straight boundary line between an adhering region and a detached region. A separator increases a distance between a first holder holding the first plate-like body and a second holder holding the second plate-like body to separate the first and second plate-like bodies.Type: ApplicationFiled: January 3, 2014Publication date: July 31, 2014Applicant: DAINIPPON SCREEN MFG. CO., LTD.Inventors: Masafumi KAWAGOE, Kazuhiro SHOJI, Yayoi SHIBAFUJI, Mikio MASUICHI, Hiroyuki UENO, Miyoshi UENO, Kazutaka TANIGUCHI
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Publication number: 20140040460Abstract: An information processing apparatus executes a process and a second server in an information processing system including a first server, the second server, and a third server. The process includes: collecting, in a first queue, traffic data that is transmitted and received by the second server; acquiring, from the first server, a client request reception time when the first server receives a request from a client and a client response time when the first server responds to the request from the client; and moving, to a second queue, traffic data of a time period from a first server request reception time when the second server receives a request from the first server after the client request reception time to a first server response time when the second server responds to the request from the first server before the client response time.Type: ApplicationFiled: June 12, 2013Publication date: February 6, 2014Inventors: Akihiko SAKURAI, Eiji Mizunuma, Atsushi Kaneko, Hideki Gou, Kazutaka Taniguchi, Takashi Yamashita, Takahiko Shirazawa
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Patent number: 8564318Abstract: A semiconductor device includes a power-supply circuit which produces a first voltage potential, a first terminal, a second terminal which receives a mode signal, an inverter which receives the mode signal and outputs an inverted mode signal, and a first transfer circuit which includes a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor coupled between the power-supply circuit and a first node, the second transistor coupled between the power-supply circuit and the first node in parallel with the first transistor, a control gate of the first transistor supplied with the inverted mode signal and a control gate of the second transistor supplied with the mode signal.Type: GrantFiled: March 14, 2013Date of Patent: October 22, 2013Assignee: Renesas Electronics CorporationInventors: Shinya Tashiro, Kazutaka Taniguchi
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Publication number: 20130135458Abstract: A carrier and a substrate are aligned even if an imager cannot be simultaneously focused on alignment marks formed on both the carrier and the substrate. Center of gravity positions G1m of an alignment pattern element AP1 on a substrate and G2m of an alignment pattern element AP2 on a transparent blanket are calculated by image processing from an image IM imaged via the blanket by a CCD camera. The position of the center of gravity Gm2 is specified by a process associated with edge extraction from the image imaged with the alignment pattern element AP2 on the blanket being in focus. High spatial frequency components are removed and low frequency components are extracted for the alignment pattern element AP1 on the substrate imaged out of focus to have a blurred outline, and the position of the center of gravity G1m is specified from an extraction result.Type: ApplicationFiled: August 30, 2012Publication date: May 30, 2013Inventors: Kazutaka TANIGUCHI, Masafumi KAWAGOE, Mikio MASUICHI, Tomoyuki KOMURA
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Publication number: 20130114074Abstract: A substrate inspection apparatus for detecting a conditionof an EBR line at a substrate edge, comprising a turntable for rotating a substrate having a film coated thereon, a light irradiator, and a photoelectric converter that receives specularly reflected light from the substrate and ouputs a captured image signal. A two-dimensional image is generation by adding detection values of electrical signals corresponding to one radial scan from a center of the substrate for one turn of a rotator, and a changing point is judged using a judgment band set along one direction of the two-dimensional image.Type: ApplicationFiled: January 6, 2012Publication date: May 9, 2013Inventors: Taigo Nakajima, Kunio Ueta, Kazutaka Taniguchi
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Patent number: 8421489Abstract: A semiconductor device includes an internal power-supply circuit which produces an internal potential, an external terminal which outputs the internal potential and inputs and outputs a signal with an outside, and a test mode signal terminal which transfers a test mode signal. The semiconductor device further includes a first CMOS transfer circuit and a second CMOS transfer circuit which are provided between the internal power-supply circuit and the external terminal, and which are controlled by the test mode signal, a clamp element which is connected between the first and second CMOS transfer circuits and suppresses a potential variation, and a delay element provided between the clamp element and the first CMOS transfer circuit.Type: GrantFiled: January 29, 2010Date of Patent: April 16, 2013Assignee: Renesas Electronics CorporationInventors: Shinya Tashiro, Kazutaka Taniguchi
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Publication number: 20120081681Abstract: A drawing device draws a pattern on a substrate by radiating light from an optical head part on a target object (for example, substrate) which relatively moves with respect to the optical head part. Here, the optical head part has a spatial modulating unit which spatially modulates light from a light source, based on pattern data, and an optical path corrector which shifts the route of light spatially modulated in the spatial modulating unit at precision subdivided more than units of spatial modulation in the spatial modulating unit (more specifically, for example, units of pixels of spatial light modulator).Type: ApplicationFiled: April 14, 2011Publication date: April 5, 2012Inventors: Yoshiyuki NAKAZAWA, Yoshio FURUYA, Ryosuke ITO, Kenji NAKANISHI, Kazutaka TANIGUCHI, Ryo YAMADA
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Publication number: 20100219855Abstract: A semiconductor device includes an internal power-supply circuit which produces an internal potential, an external terminal which outputs the internal potential and inputs and outputs a signal with an outside, and a test mode signal terminal which transfers a test mode signal. The semiconductor device further includes a first CMOS transfer circuit and a second CMOS transfer circuit which are provided between the internal power-supply circuit and the external terminal, and which are controlled by the test mode signal, a clamp element which is connected between the first and second CMOS transfer circuits and suppresses a potential variation, and a delay element provided between the clamp element and the first CMOS transfer circuit.Type: ApplicationFiled: January 29, 2010Publication date: September 2, 2010Applicant: NEC ELECTRONICS CORPORATIONInventors: Shinya Tashiro, Kazutaka Taniguchi