Patents by Inventor Kazutani Arimoto

Kazutani Arimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device for multi-bit or multi-bank architectures
    Patent number: 6249474
    Abstract: In a semiconductor memory device, global column-select lines are provided for selecting specific memory-cell arrays in accordance with select signals, and a pair of global input/output signal line is provided for each memory-cell array and connected to a pair of local input/output signal lines associated with the memory-cell array on a one-to-one basis to implement a multi-bank architecture. Alternatively, each pair of local input/output signal lines is divided into pairs of partial local input/output signal lines which are each connected to a pair of global input/output signal lines on a one-to-one basis. A memory-cell architecture is provided which has a number of data buses corresponding to an increased number of divided memory-cell arrays or memory banks to meet demands for a multi-bank and multi-bit semiconductor memory device.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: June 19, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazutani Arimoto
  • Semiconductor memory device
    Patent number: 6081443
    Abstract: In a dynamic random access memory, at a time of body-refresh operation, a bit-line potential VBL is set to a body-refresh-potential VBR, and the body-refresh-potential VBR is supplied to bit-line pairs via a bit-line precharging/equalizing circuit 111c, thereby the charge accumulated in the body of the n channel MOS transistor 72cb in a memory cell is drained to the bit-line pairs.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: June 27, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Fukashi Morishita, Shigeki Tomishima, Kazutani Arimoto
  • Semiconductor memory device
    Patent number: 5877978
    Abstract: In a dynamic random access memory, at a time of body-refresh operation, a bit-line potential VBL is set to a body-refresh-potential VBR, and the body-refresh-potential VBR is supplied to bit-line pairs via a bit-line precharging/equalizing circuit 111c, thereby the charge accumulated in the body of the n channel MOS transistor 72cb in a memory cell is drained to the bit-line pairs.
    Type: Grant
    Filed: September 13, 1996
    Date of Patent: March 2, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Fukashi Morishita, Shigeki Tomishima, Kazutani Arimoto
  • Semiconductor memory device for multi-bit or multi-bank architectures
    Patent number: 5781495
    Abstract: In a semiconductor memory device, global column-select lines are provided for selecting specific memory-cell arrays in accordance with select signals, and a pair of global input/output signal line is provided for each memory-cell array and connected to a pair of local input/output signal lines associated with the memory-cell array on a one-to-one basis to implement a multi-bank architecture. Alternatively, each pair of local input/output signal lines is divided into pairs of partial local input/output signal lines which are each connected to a pair of global input/output signal lines on a one-to-one basis. A memory-cell architecture is provided which has a number of data buses corresponding to an increased number of divided memory-cell arrays or memory banks to meet demands for a multi-bank and multi-bit semiconductor memory device.
    Type: Grant
    Filed: January 22, 1997
    Date of Patent: July 14, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazutani Arimoto