Abstract: A digital attenuator is used in a Digital Echo Suppressor to attenuate a PCM signal. This is done to decrease the influence of echo caused by both long time delay and impedance mismatching at a hybrid coil.The digital attenuator attenuates the PCM signal which is compressed by .mu. Law, when an attenuation control signal generated in the digital echo suppressor is applied to the digital attenuator. It passes the PCM signal through without attenuating it when the attenuation control signal is not applied.The attenuator consists of a plurality of pattern shift circuits and an adder or plural number of adders and a selector.The principle of the attenuation is described hereinafter;The attenuation quantity is attained from Eq. 1.Pout=.alpha. Pin (1)wherePin=input PCM signal compressed by .mu. Law.Pout=attenuated output PCM signal,.alpha.=attenuation parameter which is a real number satisfying the condition 0<.alpha.<1, and .alpha. is a summation of arbitrary numbers from 1/2.sup.1, 1/2.sup.2, 1/2.sup.

Abstract: A digital attenuator is disclosed which is capable of having the output PCM signal attenuated nearly in proportion to the input PCM signal level based upon simple logic operations ofP.sub.out = .alpha. P.sub.in + NwhereP.sub.out = output PCM signalP.sub.in = input PCM signal processed by a compressor.alpha. = a real number satisfying the condition 0 < .alpha. < 1, andN = a real number larger than or equal to 0.When N = O, in order to obtain P.sub.out = .alpha.P.sub.in, P.sub.in is shifted to the lower digit side by a predetermined number of bits by a single pattern shift cirucit, or P.sub.in is branched to the plurality of pattern shift circuits and P.sub.in is shifted to the lower digit side by predetermined number of bits respectively, which are different and the output of the pattern shift circuits are added to each other by an adder. When N > O, to obtain the sum .alpha.P.sub.in + N, the output signal .alpha.P.sub.

Abstract: The invention discloses a multiplex digital echo suppression system in which on each of the transmitting and receiving sides the PCM signal for each channel is converted into the parallel signal and also into the absolute value signal representing the absolute value of the PCM signal by eliminating the sign bit; thus converted signals are accumulated for a predetermined time in a transmitting-side and receiving side accumulators and then compared in a comparator so that the output is derived from the comparator when the accumulated signal in the transmitting-side accumulator is higher in level than the signal accumulated in the receiving-side accumulator; in response to the output signal from the comparator, a first timer is set to a first predetermined time during which the signal is derived from the first timer; when the signal level in the receiving-side accumulator is higher than a predetermined level of a threshold level comparator, the output is derived therefrom and applied to a second timer which in t

Abstract: A digital attenuator is disclosed which is capable of having the output PCM signal attenuated nearly in proportion to the input PCM signal level based upon simple logic operations ofP.sub.out = .alpha. P.sub.in + NwhereP.sub.out = output PCM signalP.sub.in = input PCM signal processed by a compressor.alpha. = a real number satisfying the condition 0 < .alpha. < 1, andN = a real number larger than or equal to 0.When N = 0, in order to obtain P.sub.out = .alpha.P.sub.in, P.sub.in is shifted to the lower digit side by a predetermined number of bits by a single pattern shift circuit, or P.sub.in is branched to the plurality of pattern shift circuits and P.sub.in is shifted to the lower digit side by predetermined number of bits respectively, which are different and the outputs of the pattern shift circuits are added to each other by an adder. When N > 0, to obtain the sum .alpha.P.sub.in + N, the output signal .alpha.P.sub.