Abstract: An image correction device generates a corrected image for a viewer with low vision, by adding excessive emphasis which reduces image quality as perceived by a viewer having normal eyesight, to at least one of luminance gradation, luminance contour, and color tone of a pre-correction image. The image correction device includes: a controller which specifies, in a low vision mode which is an image correction mode for the viewer with low vision, a parameter that represents an amount of correction greater than an upper limit of an amount of correction which does not reduce the image quality as perceived by the viewer having normal eyesight when the pre-correction image is corrected; and an image processor which generates the corrected image by correcting the at least one of the luminance gradation, the luminance contour, and the color tone of the pre-correction image with the amount of correction represented by the parameter.

Abstract: An image correction device generates a corrected image for a viewer with low vision, by adding excessive emphasis which reduces image quality as perceived by a viewer having normal eyesight, to at least one of luminance gradation, luminance contour, and color tone of a pre-correction image. The image correction device includes: a controller which specifies, in a low vision mode which is an image correction mode for the viewer with low vision, a parameter that represents an amount of correction greater than an upper limit of an amount of correction which does not reduce the image quality as perceived by the viewer having normal eyesight when the pre-correction image is corrected; and an image processor which generates the corrected image by correcting the at least one of the luminance gradation, the luminance contour, and the color tone of the pre-correction image with the amount of correction represented by the parameter.

Abstract: The data sharing apparatus in the present invention includes a first processor and a second processor, each of a different endianness, that are both connected to the memory via the data bus, in a byte order based on the endianness of the first processor. It also includes an address conversion unit which converts at least one lower bit of an address to indicate a reversed position of data in the data bus, and outputs the converted address to the memory, in the case where the second processor performs a memory access on the shared memory for data with a smaller width than the data bus.

Abstract: A semiconductor device has a processor, a first memory unit accessed by the processor, a plurality of page memory units obtained by partitioning a second memory unit which is accessible by the processor at a speed higher than the speed at which the first memory unit is accessible such that each of the page memory units has a storage capacity larger than the memory capacity of a line composing a cache memory, a tag adding, to each of the page memory units, tag information indicative of an address value in the first memory unit and priority information indicative of a replacement priority, a tag comparator for comparing, upon receipt of an access request from the processor, the address value in the first memory unit with the tag information held by the tag, and a replacement control unit for replacing the respective contents of the page memory units.

Abstract: The image processor of the present invention includes: an extracting means, an entropy decoding means, a combining means, and an inverse orthogonal transformation means. Coded data at respective stages in a certain block are extracted by the extracting means, and entropy-decoded by the entropy-decoding means, to obtain coefficient data at the respective stages in the block. The coefficient data at the respective stages are combined by the combining means to obtain coefficient data for the block. The coefficient data is subjected to inverse orthogonal transformation by the inverse orthogonal transformation means, to attain original image data for the block. The above series of processing are performed for all blocks, to attain an original image on the entire screen. The memory capacity required for combining the coefficient data at the respective stages may only be large enough to store coefficient data for one block.

Abstract: The data sharing apparatus in the present invention includes a first processor 10 and a second processor 20, each of a different endianness, that are both connected to the memory via the data bus, in a byte order based on the endianness of the first processor 10. It also includes an address conversion unit 21 which converts at least one lower bit of an address to indicate a reversed position of data in the data bus, and outputs the converted address to the memory, in the case where the second processor 20 performs a memory access on the shared memory for data with a smaller width than the data bus.

Abstract: A semiconductor device has a processor, a first memory unit accessed by the processor, a plurality of page memory units obtained by partitioning a second memory unit which is accessible by the processor at a speed higher than the speed at which the first memory unit is accessible such that each of the page memory units has a storage capacity larger than the memory capacity of a line composing a cache memory, a tag adding, to each of the page memory units, tag information indicative of an address value in the first memory unit and priority information indicative of a replacement priority, a tag comparator for comparing, upon receipt of an access request from the processor, the address value in the first memory unit with the tag information held by the tag, and a replacement control unit for replacing the respective contents of the page memory units.

Abstract: An audio-video multiplexed data generation apparatus of the present invention multiplexes spare video data encoded at a lower frame rate than that of video data together with audio and video data through a spare-video encoder and a spare-video-data storage. An audio-video multiplexed data reproducing apparatus of the present invention decodes spare video data if video decoding is not completed within a predetermined time and, when it becomes possible to complete video decoding within the predetermined time, ordinarily decodes the video data. Multiplexing the low-frame-rate spare video data together with the ordinary video data allows irregularities in reproduced video to be minimized and synchronization between audio and video data to be restored if real-time reproduction becomes difficult to accomplish.

Abstract: The image processor of the present invention includes: an extracting means, an entropy decoding means, a combining means, and an inverse orthogonal transformation means. Coded data at respective stages in a certain block are extracted by the extracting means, and entropy-decoded by the entropy-decoding means, to obtain coefficient data at the respective stages in the block. The coefficient data at the respective stages are combined by the combining means to obtain coefficient data for the block. The coefficient data is subjected to inverse orthogonal transformation by the inverse orthogonal transformation means, to attain original image data for the block. The above series of processing are performed for all blocks, to attain an original image on the entire screen. The memory capacity required for combining the coefficient data at the respective stages may only be large enough to store coefficient data for one block.

Abstract: An oriented electrically conductive polypyrrole article having a degree of orientation of at least 40% in at least one direction; an electrically conductive polypyrrole article having an electrical conductivity of at least 100 S/cm.; a process for producing an electrically conductive polypyrrole having improved electrical conductivity and stretchability, which comprises electrolytically polymerizing pyrrole and/or a pyrrole derivative in an electrolytic solution comprising an electrolyte and a solvent, said polymerization being carried out at a temperature of 0.degree. to -50.degree. C.; and a process for producing an electrically conductive polypyrrole article having improved electrical conductivity, which comprises stretching an electrically conductive polypyrrole article in at least one direction.

Abstract: A process for preparing a compound of the formula ##STR1## wherein m represents zero or 1, which comprises reacting azobenzene with nitric acid in the presence of sulfuric acid in two steps, wherein(1) the first-step reaction is carried out under the following conditions0<x.ltoreq.80,0<y.ltoreq.11, and-0.3x+12.ltoreq.y.ltoreq.-0.22x+22wherein x is the reaction temperature in .degree.C., and y is the weight ratio of sulfuric acid to water and fed into the reaction system, and(2) the second-step reaction is carried out under the following conditions0.ltoreq.x, and-(1.7/100)x+1.7.ltoreq.y.ltoreq.-(3.9/88)x+3.9.