Patents by Inventor Kazutoshi Ishii
Kazutoshi Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7351595Abstract: In a manufacturing method for a semiconductor device, a main body wafer having an interlayer insulating film is formed, and a monitor wafer on which a monitor element is formed is provided. Characteristics of the main body wafer are copied onto the monitor element by simultaneously processing the main body wafer and the monitor wafer through BPSG densification during formation of the interlayer insulating film. The characteristic of the monitor element is measured by checking a process influence of the monitor element. Manufacturing conditions are set in accordance with the process influence of the monitor element. Variations in electric characteristics of the main body wafer are reduced in accordance with the set manufacturing conditions.Type: GrantFiled: September 8, 2004Date of Patent: April 1, 2008Assignee: Seiko Instruments Inc.Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Patent number: 7335518Abstract: In a manufacturing method for a semiconductor device, a main body wafer is formed, and a monitor wafer on which a monitor element is formed is provided. Characteristics of the main body wafer are copied onto the monitor element by simultaneously processing the main body wafer and the monitor wafer. The characteristic of the monitor element is measured by checking a process influence of the monitor element. Manufacturing conditions are set in accordance with the process influence of the monitor element. Variations in electric characteristics of the main body wafer are reduced in accordance with the set manufacturing conditions.Type: GrantFiled: September 8, 2004Date of Patent: February 26, 2008Assignee: Seiko Instruments Inc.Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Patent number: 7192790Abstract: A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.Type: GrantFiled: September 8, 2004Date of Patent: March 20, 2007Assignee: Seiko Instruments Inc.Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Patent number: 7161198Abstract: An N-channel MOS transistor of a semiconductor device having a high withstand voltage employs a drain structure with a low concentration and a large diffusion depth, which causes a problem in that a sufficiently high withstand voltage cannot be obtained due to a parasitic NPN transistor formed among the drain, the well, and the semiconductor substrate which are arranged in the stated order.Type: GrantFiled: September 6, 2002Date of Patent: January 9, 2007Assignee: Seiko Instruments Inc.Inventors: Toshihiko Omi, Hitomi Watanabe, Kazutoshi Ishii, Naoto Saitoh
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Patent number: 7129099Abstract: A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.Type: GrantFiled: September 8, 2004Date of Patent: October 31, 2006Assignee: Seiko Instruments Inc.Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Patent number: 7043328Abstract: A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.Type: GrantFiled: September 8, 2004Date of Patent: May 9, 2006Assignee: Seiko Instruments Inc.Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Publication number: 20050142673Abstract: A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including, a quality check step and a condition setting step.Type: ApplicationFiled: September 8, 2004Publication date: June 30, 2005Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Publication number: 20050130332Abstract: A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.Type: ApplicationFiled: September 8, 2004Publication date: June 16, 2005Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Patent number: 6906345Abstract: Disclosed is a semiconductor device having a reduced size, increased accuracy, and flattened element isolation regions with an decreased size. A plurality of MOSFETs having gate oxide films with different thicknesses and element isolation regions are formed by a manufacturing method employing oxygen implantation. An oxygen-ion implantation process and an annealing process are applied to a method of manufacturing the semiconductor device.Type: GrantFiled: April 24, 2003Date of Patent: June 14, 2005Assignee: Seiko Instruments Inc.Inventor: Kazutoshi Ishii
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Publication number: 20050124083Abstract: A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.Type: ApplicationFiled: September 8, 2004Publication date: June 9, 2005Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Publication number: 20050124081Abstract: A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.Type: ApplicationFiled: September 8, 2004Publication date: June 9, 2005Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Publication number: 20050124082Abstract: A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.Type: ApplicationFiled: September 8, 2004Publication date: June 9, 2005Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Patent number: 6777752Abstract: In a power management semiconductor device or analog semiconductor device having a CMOS and a resistor, a conductivity type of a gate electrode of the CMOS is P-type as to both an NMOS and a PMOS, a short channel and a low threshold voltage are possible since an E-type PMOS is surface channel type, the short channel and the low threshold voltage are possible since a buried channel type NMOS is extremely shallow for the reason that arsenic having a small diffusion coefficient can be used as an impurity for threshold control, and the resistor used in a voltage dividing circuit or CR circuit is formed of polycrystalline silicon thinner than the polycrystalline silicon of the same layer as the gate electrode or a thin film metal.Type: GrantFiled: August 31, 2001Date of Patent: August 17, 2004Assignee: Seiko Instruments Inc.Inventors: Jun Osanai, Hisashi Hasegawa, Sumio Koiwa, Kazutoshi Ishii
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Patent number: 6747319Abstract: A semiconductor device including multiple high-voltage drive transistors in its output section is improved in electrostatic withstand voltage by connecting electrostatic protection transistors in parallel with the high-voltage drive transistors connected to the output pads. The drain withstand voltage of the electrostatic protection transistors is made lower than the drain withstand voltage of the high-voltage drive transistors. In addition, the channel length of electrostatic protection transistors is made short to enable efficient bipolar operation of the electrostatic protection transistors.Type: GrantFiled: March 9, 2001Date of Patent: June 8, 2004Assignee: Seiko Instruments Inc.Inventors: Yoshikazu Kojima, Kazutoshi Ishii, Masaaki Kamiya, Yasuhiro Moya
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Patent number: 6713820Abstract: A semiconductor device is provided in which each of contacts between a source and a drain of a MOS transistor and a metallic wiring is either a contact having an arbitrary one side longer than the other side, or source contacts and well contacts are made batting contacts each having an arbitrary one side of a diffusion region having the same polarity as that of a well shorter than the other side. Thus, the contact shape is longitudinal in a transistor width direction, which makes it possible that a large current is caused to flow with a small interval of gates thereof.Type: GrantFiled: April 8, 2002Date of Patent: March 30, 2004Assignee: Seiko Instruments Inc.Inventors: Toshihiko Omi, Kazutoshi Ishii
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Publication number: 20040058490Abstract: Disclosed is a semiconductor device having a reduced size, increased accuracy, and flattened element isolation regions with an decreased size. A plurality of MOSFETs having gate oxide films with different thicknesses and element isolation regions are formed by a manufacturing method employing oxygen implantation. An oxygen-ion implantation process and an annealing process are applied to a method of manufacturing the semiconductor device.Type: ApplicationFiled: April 24, 2003Publication date: March 25, 2004Applicant: SEIKO INSTRUMENTS INC.Inventor: Kazutoshi Ishii
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Patent number: 6596593Abstract: Disclosed is a semiconductor device having a reduced size, increased accuracy, and flattened element isolation regions with an decreased size. A plurality of MOSFETs having gate oxide films with different thicknesses and element isolation regions are formed by a manufacturing method employing oxygen implantation. An oxygen-ion implantation process and an annealing process are applied to a method of manufacturing the semiconductor device.Type: GrantFiled: November 30, 2001Date of Patent: July 22, 2003Assignee: Seiko Instruments Inc.Inventor: Kazutoshi Ishii
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Patent number: 6545322Abstract: There is provided a semiconductor integrated circuit device with high electrostatic resistance. A semiconductor device is provided with a transistor for input-output protection having a desired size in which its channel length is varied with respect to a channel width direction.Type: GrantFiled: October 31, 2001Date of Patent: April 8, 2003Assignee: Seiko Instruments Inc.Inventors: Kazutoshi Ishii, Toshihiko Omi
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Publication number: 20030049907Abstract: An N-channel MOS transistor of a semiconductor device having a high withstand voltage employs a drain structure with a low concentration and a large diffusion depth, which causes a problem in that a sufficiently high withstand voltage cannot be obtained due to a parasitic NPN transistor formed among the drain, the well, and the semiconductor substrate which are arranged in the stated order.Type: ApplicationFiled: September 6, 2002Publication date: March 13, 2003Inventors: Toshihiko Omi, Hitomi Watanabe, Kazutoshi Ishii, Naoto Saitoh
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Patent number: 6492680Abstract: There is provided a semiconductor integrated circuit device for driving a display element of an organic EL display device, in which an output current is controlled with high accuracy. The semiconductor integrated circuit device includes a field effect MOS transistor capable of obtaining a high accuracy output current and used for an output circuit for driving the display element of the organic EL display device, and further, a fuse trimming element is provided to its gate electrode, so that the device is constructed by the field effect MOS transistor capable of obtaining a more accurate output current. Besides, the field effect MOS transistor has such a structure that even if Vth fluctuates, fluctuation in an output current value is kept low.Type: GrantFiled: August 4, 2000Date of Patent: December 10, 2002Assignee: Seiko Instruments Inc.Inventors: Kazutoshi Ishii, Tetsuo Shioura