Patents by Inventor Kazutoshi Ohmori
Kazutoshi Ohmori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20110291280Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.Type: ApplicationFiled: August 10, 2011Publication date: December 1, 2011Inventors: Kazutoshi OHMORI, Tsuyoshi TAMARU, Naohumi OHASHI, Kiyohiko SATO, Hiroyuki MARUYAMA
-
Patent number: 8012871Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.Type: GrantFiled: April 30, 2010Date of Patent: September 6, 2011Assignee: Renesas Electronics CorporationInventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
-
Publication number: 20100210107Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.Type: ApplicationFiled: April 30, 2010Publication date: August 19, 2010Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
-
Patent number: 7723849Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.Type: GrantFiled: December 28, 2006Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
-
Publication number: 20070105369Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.Type: ApplicationFiled: December 28, 2006Publication date: May 10, 2007Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
-
Patent number: 7176121Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.Type: GrantFiled: October 15, 2003Date of Patent: February 13, 2007Assignee: Renesas Technology Corp.Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
-
Patent number: 6812127Abstract: An interlayer dielectric film that surrounds via holes for connecting wirings of a second wiring layer and the wirings of third wiring layer is constituted of a dielectric material having a relatively smaller Young's modulus compared with the Young's modulus of a dielectric material constituting a dielectric film that surrounds wiring grooves in dual damascene wirings, which can improve the heat resistance and electromigration resistance of the dual damascene wirings.Type: GrantFiled: November 16, 2001Date of Patent: November 2, 2004Assignee: Renesas Technology Corp.Inventors: Takayuki Oshima, Hiroshi Miyazaki, Hideo Aoki, Kazutoshi Ohmori
-
Publication number: 20040192032Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.Type: ApplicationFiled: October 15, 2003Publication date: September 30, 2004Applicant: Renesas Technology Corp.Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
-
Publication number: 20040152336Abstract: Disclosed here is a method for manufacturing a semiconductor device, which can prevent films from delamination and improve the reliability of the semiconductor. A first insulating film comprising a silicon carbide film, silicon carbide nitride film, or silicon oxide nitride film is formed as a barrier insulating film of the wiring, and then a second insulating film comprising a fluorine containing silicon oxide film is formed on the first insulating film by a high density plasma CVD method as a low permittivity insulating film. And, when forming the second insulating film, the semiconductor substrate is heated up to a predetermined deposition temperature using a heat-up plasma generated by a gas containing no oxygen such as an argon plasma. When the substrate reaches the predetermined deposition temperature, the insulating film deposition gas is introduced into the deposition chamber to deposit the second insulating film on the first insulating film.Type: ApplicationFiled: January 7, 2004Publication date: August 5, 2004Applicant: Renesas Technology Corp.Inventors: Noriko Miura, Kazutoshi Ohmori, Kiyohiko Sato, Junji Noguchi, Tsuyoshi Tamaru
-
Patent number: 6767782Abstract: Charge-up damages to a substrate are reduced in a manufacturing process using plasma, and the reliability of a semiconductor device is improved. By forming an insulating film on the back of a substrate before a step of forming a first wiring layer, even if a plasma CVD method, a sputtering method, or a dry-etching method is used in a wiring-forming step executed later, then it is possible to suppress electric charges which are generated on the substrate and which flow to the ground potential through the substrate, and to prevent damages to the substrate due to charge-up.Type: GrantFiled: February 26, 2002Date of Patent: July 27, 2004Assignees: Renesas Technology Corp., Hitachi Tokyo Electronics Co., Ltd.Inventors: Takeshi Saikawa, Ryohei Maeno, Sadayuki Okudaira, Tetsuo Saito, Tsuyoshi Tamaru, Kazutoshi Ohmori
-
Publication number: 20020168827Abstract: Charge-up damages to a substrate are reduced in a manufacturing process using plasma, and the reliability of a semiconductor device is improved.Type: ApplicationFiled: February 26, 2002Publication date: November 14, 2002Applicant: Hitachi, Ltd.Inventors: Takeshi Saikawa, Ryohei Maeno, Sadayuki Okudaira, Tetsuo Saito, Tsuyoshi Tamaru, Kazutoshi Ohmori
-
Publication number: 20020100984Abstract: An interlayer dielectric film that surrounds via holes for connecting wirings of a second wiring layer and the wirings of a third wiring layer is constituted of a dielectric material having a relatively smaller Young's modulus compared with the Young's modulus of a dielectric material constituting a dielectric film that surrounds wiring grooves in dual damascene wirings, which can improve the heat resistance and electromigration resistance of the dual damascene wirings.Type: ApplicationFiled: November 16, 2001Publication date: August 1, 2002Applicant: Hitachi, Ltd.Inventors: Takayuki Oshima, Hiroshi Miyazaki, Hideo Aoki, Kazutoshi Ohmori