Patents by Inventor Kazutoshi Oku
Kazutoshi Oku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8110878Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.Type: GrantFiled: July 8, 2011Date of Patent: February 7, 2012Assignee: Renesas Electronics CorporationInventors: Naozumi Morino, Atsushi Hiraiwa, Kazutoshi Oku, Toshiaki Ito, Motoshige Igarashi, Takayuki Sasaki, Masao Sugiyama, Hiroshi Yanagita, Shinichi Watarai
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Publication number: 20110266631Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.Type: ApplicationFiled: July 8, 2011Publication date: November 3, 2011Inventors: Naozumi MORINO, Atsushi HIRAIWA, Kazutoshi OKU, Toshiaki ITO, Motoshige IGARASHI, Takayuki SASAKI, Masao SUGIYAMA, Hiroshi YANAGITA, Shinichi WATARAI
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Patent number: 7982271Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.Type: GrantFiled: October 11, 2010Date of Patent: July 19, 2011Assignee: Renesas Electronics CorporationInventors: Naozumi Morino, Atsushi Hiraiwa, Kazutoshi Oku, Toshiaki Ito, Motoshige Igarashi, Takayuki Sasaki, Masao Sugiyama, Hiroshi Yanagita, Shinichi Watarai
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Publication number: 20110024847Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.Type: ApplicationFiled: October 11, 2010Publication date: February 3, 2011Inventors: NAOZUMI MORINO, Atsushi Hiraiwa, Kazutoshi Oku, Toshiaki Ito, Motoshige Igarashi, Takayuki Sasaki, Masao Sugiyama, Hiroshi Yanagita, Shinichi Watarai
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Patent number: 7821076Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.Type: GrantFiled: April 12, 2009Date of Patent: October 26, 2010Assignee: Renesas Electronics CorporationInventors: Naozumi Morino, Atsushi Hiraiwa, Kazutoshi Oku, Toshiaki Ito, Motoshige Igarashi, Takayuki Sasaki, Masao Sugiyama, Hiroshi Yanagita, Shinichi Watarai
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Publication number: 20090278204Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.Type: ApplicationFiled: April 12, 2009Publication date: November 12, 2009Inventors: Naozumi MORINO, Atsushi HIRAIWA, Kazutoshi OKU, Toshiaki ITO, Motoshige IGARASHI, Takayuki SASAKI, Masao SUGIYAMA, Hiroshi YANAGITA, Shinichi WATARAI
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Publication number: 20090179247Abstract: A technique which can improve manufacturing yield and product reliability is provided in a semiconductor device having a triple well structure. An inverter circuit which includes an n-channel type field effect transistor formed in a shallow p-type well and a p-channel type field effect transistor formed in a shallow n-type well, and does not contribute to circuit operations is provided in a deep n-type well formed in a p-type substrate; the shallow p-type well is connected to the substrate using a wiring of a first layer; and the gate electrode of the p-channel type field effect transistor and the gate electrode of the n-channel type field effect transistor are connected to the shallow n-type well using a wiring of an uppermost layer.Type: ApplicationFiled: January 15, 2009Publication date: July 16, 2009Inventors: Masako FUJII, Shigeki Obayashi, Naozumi Morino, Atsushi Hiraiwa, Shinichi Watarai, Takeshi Yoshida, Kazutoshi Oku, Masao Sugiyama, Yoshinori Kondo, Yuichi Egawa, Yoshiyuki Kaneko
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Patent number: 5394013Abstract: A bonding pad comprises a central film and a peripheral film. The peripheral film is formed around the central film, including a film formed at the same time as the central film, and being continuous with the central film. The level of the central film is made equal to or higher than the level of a protective film on the peripheral film by central film raising means. Therefore, even if the wire moves in a lateral direction when the tip of a wire is pressed against the central film, the tip of the wire does not collide with the protective film. Accordingly, it is possible to avoid the case where cracks are generated in the surface protecting film during wire bonding because of a lateral movement of the wire.Type: GrantFiled: September 22, 1993Date of Patent: February 28, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazutoshi Oku, Masahiro Hirosue
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Patent number: 5354702Abstract: A method for manufacturing an EEPROM comprises the step of using raw gas containing an organic compound having a molecular weight of more than 44, such as ethyl acetate and tetrahydrofuran when a first polysilicon layer serving as a select gate electrode and a second polysilicon layer serving as a floating gate electrode are deposited by a CVD process. The above described step allows a voltage at the time of tunneling electrons to be decreased.Type: GrantFiled: July 1, 1993Date of Patent: October 11, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Eiichi Arima, Akira Nishimoto, Shinichi Jintate, Kazuo Sudo, Kazutoshi Oku
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Patent number: 5252847Abstract: A method for manufacturing an EEPROM comprises the step of using raw gas containing an organic compound having a molecular weight of more than 44, such as ethyl acetate and tetrahydrofuran when a first polysilicon layer serving as a select gate electrode and a second polysilicon layer serving as a floating gate electrode are deposited by a CVD process. The above described step allows a voltage at the time of tunneling electrons to be decreased.Type: GrantFiled: September 8, 1988Date of Patent: October 12, 1993Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Eiichi Arima, Akira Nishimoto, Shinichi Jintate, Kazuo Sudo, Kazutoshi Oku