Patents by Inventor Kazutoshi Wakao
Kazutoshi Wakao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8379887Abstract: A vibrating electrode plate that senses a sound pressure faces a counter electrode plate to constitute a capacitance type acoustic sensor. In the counter electrode plate, acoustic perforations are opened in order to pass vibration, and plural projections are provided on a surface facing the vibrating electrode plate. An interval between the projections is decreased in a region where the vibrating electrode plate has high flexibility to easily generate local sticking with the counter electrode plate. The interval between the projections is increased in a region where the vibrating electrode plate has low flexibility to hardly generate local sticking with the counter electrode plate. The projections thus arranged prevent firm fixing of the vibrating electrode plate to the counter electrode plate and interruption of vibration of the vibrating electrode plate.Type: GrantFiled: January 30, 2008Date of Patent: February 19, 2013Assignee: OMRON CorporationInventors: Takashi Kasai, Kazutoshi Wakao, Takeshi Matsuo, Takayoshi Onishi, Akane Takahashi
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Publication number: 20100175477Abstract: A vibrating electrode plate 24 that senses a sound pressure faces a counter electrode plate 25 to constitute a capacitance type acoustic sensor. In the counter electrode plate 25, acoustic perforations 31 are opened in order to pass vibration, and plural projections 36 are provided on a surface facing the vibrating electrode plate 24. An interval between the projections 36 is decreased in a region where the vibrating electrode plate 24 has high flexibility to easily generate local sticking with the counter electrode plate 25. The interval between the projections 36 is increased in a region where the vibrating electrode plate 24 has low flexibility to hardly generate local sticking with the counter electrode plate 25. The projections thus arranged prevent firm fixing of the vibrating electrode plate to the counter electrode plate and interruption of vibration of the vibrating electrode plate.Type: ApplicationFiled: January 30, 2008Publication date: July 15, 2010Applicant: OMRON CORPORATIONInventors: Takashi Kasai, Kazutoshi Wakao, Takeshi Matsuo, Takayoshi Onishi, Akane Takahashi
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Publication number: 20040229427Abstract: A pointed shape may be present on the top end of the capacitor bottom (lower) electrode of a cylindrical capacitor. To cover this pointed end, a two-layer dielectric film of a capacitor dielectric film and another capacitor dielectric film is formed. As a result, while the capacitor bottom electrode has a pointed shape on its top end, the dielectric film covering the portion having a pointed shape has a greater thickness than the dielectric film covering the other parts of the vertical portion. Thus, even if the portion with a pointed shape on the capacitor bottom electrode has a concentration of electric field, the dielectric film exhibits a sufficient insulation performance to prevent leakage current. In this way, a semiconductor device is provided with an improved property of a capacitor dielectric film by the reduction of the risk of generating a leakage current in the capacitor dielectric film.Type: ApplicationFiled: October 23, 2003Publication date: November 18, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Kazutoshi Wakao, Junichi Tsuchimoto, Yutaka Inaba, Kazuhiro Aihara
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Patent number: 6734488Abstract: A semiconductor device with a capacitor having a charge retaining capability improved by preventing generation of a leakage current in a capacitor dielectric film, and a manufacturing method of the same are provided. An indium oxide film is formed to continuously cover the upper surfaces of a tungsten film and an interlayer oxide film. A tantalum oxide film is formed to continuously cover the surface of the indium oxide film and a portion of the upper surface of the interlayer oxide film. Another indium oxide film is formed to cover the upper surface of the tantalum oxide film.Type: GrantFiled: February 7, 2000Date of Patent: May 11, 2004Assignee: Renesas Technology Corp.Inventors: Kazuhiro Aihara, Junichi Tsuchimoto, Yutaka Inaba, Kazutoshi Wakao
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Patent number: 6649969Abstract: The invention provides a nonvolatile semiconductor device, or the like. According to the fabrication process of the present invention, silica glass containing boron or phosphorous is used as a material of high absorbency, which is treated in the vapor phase HF atmosphere and, therefore, selective etching of silica glass, only, of high absorbency becomes possible so that a void area can be formed beneath the fin of the floating gate. Accordingly, the absolute value of the parasitic capacitance between the floating gate and the substrate is decreased. In addition, the degree of the fluctuation of the parasitic capacitance due to the manufacturing process can be restricted to a low level. Accordingly, a nonvolatile semiconductor device of high performance can be gained without lowering the yield.Type: GrantFiled: July 20, 2001Date of Patent: November 18, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Naoki Tsuji, Akinobu Teramoto, Kazutoshi Wakao
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Patent number: 6472700Abstract: A semiconductor device capable of suppressing increase in the junction leakage current and preventing deterioration in the electric characteristics even when the device is miniaturized, and a method of manufacturing thereof are attained. The semiconductor device includes a semiconductor substrate, an isolation insulator, a gate electrode, a coating film, an interlayer insulation film, and a sidewall coating film. The semiconductor substrate has a main surface. The isolation insulator is formed at the main surface of the semiconductor substrate and isolates a conductive region. The gate electrode is formed in the conductive region. The coating film is formed on the isolation insulator, and it has a sidewall and a film thickness of at most that of the gate electrode. The interlayer insulation film is formed on the coating film. The sidewall coating film is formed on the sidewall of the coating film, and it includes a material having an etching rate different from that of the interlayer insulation film.Type: GrantFiled: June 16, 1999Date of Patent: October 29, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazutoshi Wakao, Akinobu Teramoto, Masahiko Fujisawa
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Publication number: 20020100928Abstract: The invention provides a nonvolatile semiconductor device, or the like. According to the fabrication process of the present invention, silica glass containing boron or phosphorous is used as a material of high absorbency, which is treated in the vapor phase HF atmosphere and, therefore, selective etching of silica glass, only, of high absorbency becomes possible so that a void area can be formed beneath the fin of the floating gate. Accordingly, the absolute value of the parasitic capacitance between the floating gate and the substrate is decreased. In addition, the degree of the fluctuation of the parasitic capacitance due to the manufacturing process can be restricted to a low level. Accordingly, a nonvolatile semiconductor device of high performance can be gained without lowering the yield.Type: ApplicationFiled: July 20, 2001Publication date: August 1, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Naoki Tsuji, Akinobu Teramoto, Kazutoshi Wakao
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Publication number: 20020027260Abstract: A semiconductor device capable of suppressing increase in the junction leakage current and preventing deterioration in the electric characteristics even when the device is miniaturized, and a method of manufacturing thereof are attained. The semiconductor device includes a semiconductor substrate, an isolation insulator, a gate electrode, a coating film, an interlayer insulation film, and a sidewall coating film. The semiconductor substrate has a main surface. The isolation insulator is formed at the main surface of the semiconductor substrate and isolates a conductive region. The gate electrode is formed in the conductive region. The coating film is formed on the isolation insulator, and it has a sidewall and a film thickness of at most that of the gate electrode. The interlayer insulation film is formed on the coating film. The sidewall coating film is formed on the sidewall of the coating film, and it includes a material having an etching rate different from that of the interlayer insulation film.Type: ApplicationFiled: June 16, 1999Publication date: March 7, 2002Inventors: KAZUTOSHI WAKAO, AKINOBU TERAMOTO, MASAHIKO FUJISAWA
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Patent number: 6174783Abstract: The front surface of a semiconductor substrate is formed with a trench. An insulating film is formed on the front surface of the semiconductor substrate including the trench while the bottom of the trench is kept at a higher temperature than the surface opening of the trench. To this end, the back surface of the semiconductor substrate is kept at a higher temperature than the front surface. This is done by heating the back surface of the semiconductor substrate with a halogen lamp. Alternatively, the front surface temperature is made lower than the back surface temperature by blowing a gas for forming an insulating film against the front surface of the semiconductor substrate.Type: GrantFiled: July 23, 1998Date of Patent: January 16, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Kazutoshi Wakao