Patents by Inventor Kazuya FUKASE

Kazuya FUKASE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10971592
    Abstract: A semiconductor device includes a gate insulating film on a semiconductor substrate, and a gate electrode on the gate insulating film. The gate electrode includes a first layer containing polycrystalline silicon, a second layer between the first layer and the gate insulating film and containing polycrystalline silicon and carbon, a third layer on an upper surface of the first layer and containing polycrystalline silicon and carbon, a fourth layer on a first side surface of the first layer and containing polycrystalline silicon and carbon, and a fifth layer on a second side surface of the first layer and containing polycrystalline silicon and carbon.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: April 6, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kazuya Fukase
  • Publication number: 20200066862
    Abstract: A semiconductor device includes a gate insulating film on a semiconductor substrate, and a gate electrode on the gate insulating film. The gate electrode includes a first layer containing polycrystalline silicon, a second layer between the first layer and the gate insulating film and containing polycrystalline silicon and carbon, a third layer on an upper surface of the first layer and containing polycrystalline silicon and carbon, a fourth layer on a first side surface of the first layer and containing polycrystalline silicon and carbon, and a fifth layer on a second side surface of the first layer and containing polycrystalline silicon and carbon.
    Type: Application
    Filed: February 19, 2019
    Publication date: February 27, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Kazuya FUKASE
  • Publication number: 20160380115
    Abstract: A thin film transistor includes semiconductor layer, source electrode, and drain electrode. The semiconductor layer includes first to fifth regions. The third region is provided between the first and second regions. The first region is disposed between the fourth and third regions. The second region is disposed between the fifth and third regions. The semiconductor layer includes an oxide. The source electrode is connected to the first region. The drain electrode is connected to the second region. First thickness of the first region along a second direction is thinner than third thickness along the second direction of each of the third to fifth regions. The second direction crosses a first direction and connects the first region and the source electrode. The first direction connects the first and second regions. Second thickness of the second region along the second direction is thinner than the third thickness.
    Type: Application
    Filed: September 7, 2016
    Publication date: December 29, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shintaro NAKANO, Yuya MAEDA, Tatsuya OHGURO, Hisayo MOMOSE, Tetsu MOROOKA, Kazuya FUKASE, Nobuki KANREI
  • Publication number: 20160284746
    Abstract: According to one embodiment, a solid-state imaging device includes a plurality of photoelectric conversion elements, a field effect transistor, a trench, and a P-type impurity diffusion region. The plurality of photoelectric conversion elements is two-dimensionally arranged in a semiconductor layer. The field effect transistor includes N-type source and drain on a surface side of the semiconductor layer. The trench penetrates through a surface and a rear surface of the semiconductor layer and surrounds each of the photoelectric conversion elements. The width of the trench is enlarged from the surface of the semiconductor layer toward a position at a predetermined depth, and is not enlarged at a position deeper than the position at the predetermined depth. The P-type impurity diffusion region is arranged in a side surface of the trench.
    Type: Application
    Filed: June 19, 2015
    Publication date: September 29, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuya FUKASE, Tatsuya OHGURO, Hisayo MOMOSE, Tetsu MOROOKA, Takahisa KANEMURA
  • Patent number: 9318615
    Abstract: A semiconductor device according to an embodiment includes a gate electrode, a first dielectric film, an oxide semiconductor film, a second dielectric film, a source electrode and a drain electrode. The first dielectric film is placed above the gate electrode. The oxide semiconductor film is placed above the first dielectric film. The oxide semiconductor film is formed to have a film thickness in a first contact region in contact with the source electrode and a second contact region in contact with the drain electrode larger than a film thickness in a channel region of the oxide semiconductor film so that a film portion of the first contact region projects toward the source electrode side and a film portion of the second contact region projects toward the drain electrode side.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: April 19, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuya Ohguro, Hisayo Momose, Tetsu Morooka, Kazuya Fukase
  • Publication number: 20160093742
    Abstract: A semiconductor device according to an embodiment, includes a gate electrode, a first dielectric film, a first oxide semiconductor film, a second dielectric film, a source electrode, a source wire, a drain electrode, and a drain wire. The source wire is arranged on the second dielectric film, and connected to the source electrode. The drain wire is arranged on the second dielectric film, and connected to the drain electrode. At least one of the source wire and the drain wire includes a fringe portion sticking out above a channel region. A barrier film that suppresses intrusion of hydrogen is arranged being in contact with at least one of an upper surface and a lower surface of the fringe portion. A region where the barrier film is not formed is included above the channel region.
    Type: Application
    Filed: March 19, 2015
    Publication date: March 31, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hisayo MOMOSE, Tatsuya OHGURO, Tetsu MOROOKA, Kazuya FUKASE, Shintaro NAKANO, Yuya MAEDA, Shuichi TORIYAMA, Nobuki KANREI
  • Patent number: 9196698
    Abstract: A semiconductor device according to an embodiment, includes a source electrode, a drain electrode arranged apart from the source electrode, an oxide semiconductor film, a gate dielectric film, and a gate electrode. The oxide semiconductor film is arranged below the source electrode and the drain electrode to connect the source electrode and the drain electrode. The gate dielectric film is formed below the oxide semiconductor film such that a thickness below at least one of the source electrode and the drain electrode is made thinner than a thickness below a channel region of the oxide semiconductor film between the source electrode and the drain electrode. The gate electrode is arranged below the gate dielectric film and formed in a position where one of portions of the gate electrode overlaps with the source electrode and another one of the portions of the gate electrode overlaps with the drain electrode.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: November 24, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuya Fukase, Tatsuya Ohguro, Hisayo Momose, Tetsu Morooka
  • Publication number: 20150249156
    Abstract: A semiconductor device according to an embodiment includes a gate electrode, a first dielectric film, an oxide semiconductor film, a second dielectric film, a source electrode and a drain electrode. The first dielectric film is placed above the gate electrode. The oxide semiconductor film is placed above the first dielectric film. The oxide semiconductor film is formed to have a film thickness in a first contact region in contact with the source electrode and a second contact region in contact with the drain electrode larger than a film thickness in a channel region of the oxide semiconductor film so that a film portion of the first contact region projects toward the source electrode side and a film portion of the second contact region projects toward the drain electrode side.
    Type: Application
    Filed: June 27, 2014
    Publication date: September 3, 2015
    Inventors: Tatsuya OHGURO, Hisayo MOMOSE, Tetsu MOROOKA, Kazuya FUKASE
  • Publication number: 20150048359
    Abstract: A semiconductor device according to an embodiment, includes a source electrode, a drain electrode arranged apart from the source electrode, an oxide semiconductor film, a gate dielectric film, and a gate electrode. The oxide semiconductor film is arranged below the source electrode and the drain electrode to connect the source electrode and the drain electrode. The gate dielectric film is formed below the oxide semiconductor film such that a thickness below at least one of the source electrode and the drain electrode is made thinner than a thickness below a channel region of the oxide semiconductor film between the source electrode and the drain electrode. The gate electrode is arranged below the gate dielectric film and formed in a position where one of portions of the gate electrode overlaps with the source electrode and another one of the portions of the gate electrode overlaps with the drain electrode.
    Type: Application
    Filed: December 12, 2013
    Publication date: February 19, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuya FUKASE, Tatsuya OHGURO, Hisayo MOMOSE, Tetsu MOROOKA
  • Publication number: 20140246666
    Abstract: In general, according to one embodiment, a semiconductor device includes a first electrode, an oxide semiconductor film, an insulating film, a second electrode, a third electrode. The oxide semiconductor film is configured together with a first region, a second region, a third region, a fourth region, and a fifth region in one direction. The insulating film is provided between the first electrode and the oxide semiconductor film. The second electrode is provided on the second region and contacts the second region with an entire upper face of the second region as a contact face. The third electrode is provided on the fourth region and contacts the fourth region with an entire upper face of the fourth region as a contact face. The oxygen concentrations in the second region and in the fourth region are less than the oxygen concentration in the third region.
    Type: Application
    Filed: July 3, 2013
    Publication date: September 4, 2014
    Applicants: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsu MOROOKA, Tatsuya OHGURO, Hisayo MOMOSE, Kazuya FUKASE
  • Publication number: 20140239289
    Abstract: In general, according to one embodiment, a semiconductor device includes a first electrode, an oxide semiconductor film, an insulating film, a first protective film, second and third electrodes. The oxide semiconductor film is provided on the first electrode. The oxide semiconductor film includes a first face on the first electrodes side and a second face on a side opposite to the first face. The insulating film is provided between the first electrode and the oxide semiconductor film. The first protective film includes a first film provided between the insulating film and the first face and a second film provided on the second face. The first protective film suppresses substances including hydrogen from being introduced from an outer side of the oxide semiconductor film to an inner side of the oxide semiconductor film. The second electrode and the third electrode are electrically connected to the oxide semiconductor film.
    Type: Application
    Filed: June 25, 2013
    Publication date: August 28, 2014
    Applicants: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsu MOROOKA, Tatsuya OHGURO, Hisayo MOMOSE, Kazuya FUKASE