Abstract: A semiconductor device having a transistor gate length greatly reduced as a result of promotion of semiconductor integrated circuit miniaturization where leakage current generation in a gate insulating film can be inhibited to enhance the transistor function. The semiconductor device includes: a semiconductor substrate having a main surface; a pair of source/drain regions formed over the main surface of the semiconductor substrate; a gate insulating film formed, over a region between the pair of source/drain regions, to be in contact with the main surface; and a gate electrode formed to be in contact with the upper surface of the gate insulating film. In the semiconductor device, the gate electrode has a length of less than 45 nm in a direction from a first one of the pair of source/drain regions to a second one of the pair of source/drain regions, and the gate insulating film has an antiferroelectric film.

Abstract: A semiconductor integrated circuit and a pattern lay-outing method for the same are disclosed, which can suppress bending or partial drop-out of a dummy pattern even when a mechanical stress acts on the dummy pattern in CMP. The semiconductor integrated circuit includes predetermined functional areas and a dummy pattern formed in a space area. The space area is positioned between predetermined functional areas. The dummy pattern includes a first metal portion formed in the shape of a frame and defining an outer edge of the dummy pattern, a second metal portion positioned on an inner periphery side of the first metal portion and formed so as to be continuous with the first metal portion, and a plurality of non-forming areas positioned in an area where the second metal portion is not formed on the inner periphery side of the first metal portion.

Abstract: A semiconductor integrated circuit and a pattern lay-outing method for the same are disclosed, which can suppress bending or partial drop-out of a dummy pattern even when a mechanical stress acts on the dummy pattern in CMP. The semiconductor integrated circuit includes predetermined functional areas and a dummy pattern formed in a space area. The space area is positioned between predetermined functional areas. The dummy pattern includes a first metal portion formed in the shape of a frame and defining an outer edge of the dummy pattern, a second metal portion positioned on an inner periphery side of the first metal portion and formed so as to be continuous with the first metal portion, and a plurality of non-forming areas positioned in an area where the second metal portion is not formed on the inner periphery side of the first metal portion.

Abstract: A semiconductor integrated circuit and a pattern lay-outing method for the same are disclosed, which can suppress bending or partial drop-out of a dummy pattern even when a mechanical stress acts on the dummy pattern in CMP. The semiconductor integrated circuit includes predetermined functional areas and a dummy pattern formed in a space area. The space area is positioned between predetermined functional areas. The dummy pattern includes a first metal portion formed in the shape of a frame and defining an outer edge of the dummy pattern, a second metal portion positioned on an inner periphery side of the first metal portion and formed so as to be continuous with the first metal portion, and a plurality of non-forming areas positioned in an area where the second metal portion is not formed on the inner periphery side of the first metal portion.

Abstract: A semiconductor device having a transistor gate length greatly reduced as a result of promotion of semiconductor integrated circuit miniaturization where leakage current generation in a gate insulating film can be inhibited to enhance the transistor function. The semiconductor device includes: a semiconductor substrate having a main surface; a pair of source/drain regions formed over the main surface of the semiconductor substrate; a gate insulating film formed, over a region between the pair of source/drain regions, to be in contact with the main surface; and a gate electrode formed to be in contact with the upper surface of the gate insulating film. In the semiconductor device, the gate electrode has a length of less than 45 nm in a direction from a first one of the pair of source/drain regions to a second one of the pair of source/drain regions, and the gate insulating film has an antiferroelectric film.

Abstract: A semiconductor integrated circuit and a pattern lay-outing method for the same are disclosed, which can suppress bending or partial drop-out of a dummy pattern even when a mechanical stress acts on the dummy pattern in CMP. The semiconductor integrated circuit includes predetermined functional areas and a dummy pattern formed in a space area. The space area is positioned between predetermined functional areas. The dummy pattern includes a first metal portion formed in the shape of a frame and defining an outer edge of the dummy pattern, a second metal portion positioned on an inner periphery side of the first metal portion and formed so as to be continuous with the first metal portion, and a plurality of non-forming areas positioned in an area where the second metal portion is not formed on the inner periphery side of the first metal portion.

Abstract: A simulator is provided which can simulate in consideration of various parameters in a CMP process. A pattern density two-dimensional distribution calculating part takes a pattern density two-dimensional distribution image. A mesh adjusting part performs a mesh adjustment of a measured data. A height distribution calculating part calculates a height distribution based on the pattern density two-dimensional distribution image. A correlation coefficient calculating part calculates a correlation coefficient by performing a least squares analysis of a measured data and a height distribution data. Passing through a Fourier calculation part, spatial filter part, and reverse Fourier calculating part, the pattern density two-dimensional distribution image becomes a pattern density two-dimensional distribution image. This distribution image further passes through a height distribution calculating part, resulting in a height distribution data.

Abstract: There are saved layout data which have parent cell information indicative of higher order cell data to directly refer to low order cell data (or basic element data), thereby defining a reverse hierarchical structure. More specifically, both of basic element data (figD1 and figD2) have cell data (cell2) as the parent cell information, all of basic element data (figD3 to figD5) have cell data (cell3) as the parent cell information, the cell data (cell3) have two identical cell data (cell2 and cell2) as the parent cell information, and the cell data (cell2) have three identical cell data (cell3, cell3 and cell3) as the parent cell information.

Abstract: A projection aligner of the present invention, in which ultraviolet light emitted from a lamp housing is split by a fly-eye lens into a large number of point light sources which are independent of one another. Further, in this projection aligner, the light is shaped by an aperture, so that a secondary light source plane is formed. Moreover, after an exposure area is established by a blind, a photomask is illuminated. Thereafter, an image of a light source is formed on a pupillary surface of a projection optical system from light diffracted by the photomask. Furthermore, a wave front aberration is compensated by an aberration eliminating filter placed on the pupillary surface of the optical system of the projection aligner. Then, the image of a circuit pattern is formed on a wafer. Thereby, the influence of the aberration of the optical system is eliminated. Consequently, the high-accuracy transferring of the pattern can be achieved.

Abstract: Provided is a mask data processor capable of expanding a design data throughout the entire area of a mask. A storage device (MR) inputs a design data of sub-chips (D1) and mask data creation specification data (D2) to a pattern-density data generation device (10). Then, a data execution part (11) performs an arithmetic execution to the design data of sub-chips (D1) based on the mask data creation specification data (D2), followed by automatic mask data generation processing, layer arithmetic execution processing, and dummy pattern generation processing. When calculating a pattern graphic area, a graphic area calculation part (12) eliminates any overlap between graphics in order to avoid duplicate calculation. Based on the pattern graphic area, a pattern-density data calculation part (13) calculates the area ratios of graphic elements, i.e., pattern elements, contained in a unit region.

Abstract: A projection aligner of the present invention, in which ultraviolet light emitted from a lamp housing is split by a fly-eye lens into a large number of point light sources which are independent of one another. Further, in this projection aligner, the light is shaped by an aperture, so that a secondary light source plane is formed. Moreover, after an exposure area is established by a blind, a photomask is illuminated. Thereafter, an image of a light source is formed on a pupillary surface of a projection optical system from light diffracted by the photomask. Furthermore, a wave front aberration is compensated by an aberration eliminating filter placed on the pupillary surface of the optical system of the projection aligner. Then, the image of a circuit pattern is formed on a wafer. Thereby, the influence of the aberration of the optical system is eliminated. Consequently, the high-accuracy transferring of the pattern can be achieved.

Abstract: There are saved layout data which have parent cell information indicative of higher order cell data to directly refer to low order cell data (or basic element data), thereby defining a reverse hierarchical structure. More specifically, both of basic element data (figD1 and figD2) have cell data (cell2) as the parent cell information, all of basic element data (figD3 to figD5) have cell data (cell3) as the parent cell information, the cell data (cell3) have two identical cell data (cell2 and cell2) as the parent cell information, and the cell data (cell2) have three identical cell data (cell3, cell3 and cell3) as the parent cell information.

Abstract: A projection aligner of the present invention, in which ultraviolet light emitted from a lamp housing is split by a fly-eye lens into a large number of point light sources which are independent of one another. Further, in this projection aligner, the light is shaped by an aperture, so that a secondary light source plane is formed. Moreover, after an exposure area is established by a blind, a photomask is illuminated. Thereafter, an image of a light source is formed on a pupillary surface of a projection optical system from light diffracted by the photomask. Furthermore, a wave front aberration is compensated by an aberration eliminating filter placed on the pupillary surface of the optical system of the projection aligner. Then, the image of a circuit pattern is formed on a wafer. Thereby, the influence of the aberration of the optical system is eliminated. Consequently, the high-accuracy transferring of the pattern can be achieved.

Abstract: There are saved layout data which have parent cell information indicative of higher order cell data to directly refer to low order cell data (or basic element data), thereby defining a reverse hierarchical structure. More specifically, both of basic element data (figD1 and figD2) have cell data (cell2) as the parent cell information, all of basic element data (figD3 to figD5) have cell data (cell3) as the parent cell information, the cell data (cell3) have two identical cell data (cell2 and cell2) as the parent cell information, and the cell data (cell2) have three identical cell data (cell3, cell3 and cell3) as the parent cell information.

Abstract: A mask data correction apparatus that can increase efficiency of processing while maintaining high accuracy by effectively using the hierarchical structure of a layout data: A Fourier transformation part performs Fourier transformation of base elements defined by the layout data to obtain Fourier images of the base elements. A synthesizing part superimposes, based on the hierarchical structure, the Fourier images of the base elements in Fourier space, to obtain a Fourier image of the entire graphic. A spatial filter part subjects the Fourier image of the entire graphic to spatial filter processing that corresponds to distortion expected in a manufacturing process. An inverse Fourier transformation part performs inverse Fourier transformation of the Fourier image after spatial filter processing, to obtain the inverse Fourier image reflecting the distortion.

Abstract: A simulator is provided which can simulate in consideration of various parameters in a CMP process. A pattern density two-dimensional distribution calculating part takes a pattern density two-dimensional distribution image. A mesh adjusting part performs a mesh adjustment of a measured data. A height distribution calculating part calculates a height distribution based on the pattern density two-dimensional distribution image. A correlation coefficient calculating part calculates a correlation coefficient by performing a least squares analysis of a measured data and a height distribution data. Passing through a Fourier calculation part, spatial filter part, and reverse Fourier calculating part, the pattern density two-dimensional distribution image becomes a pattern density two-dimensional distribution image. This distribution image further passes through a height distribution calculating part, resulting in a height distribution data.

Abstract: A photomask fabricated by a photomask fabrication method has a transparent substrate (10), a shade pattern (11) formed in a hollow section (23), and a phase shift pattern (102) having a flat surface that is selectively formed on the transparent substrate (10) and the shield pattern (11).

Abstract: Provided is a mask data processor capable of expanding a design data throughout the entire area of a mask. A storage device (MR) inputs a design data of sub-chips (D1) and mask data creation specification data (D2) to a pattern-density data generation device (10). Then, a data execution part (11) performs an arithmetic execution to the design data of sub-chips (D1) based on the mask data creation specification data (D2), followed by automatic mask data generation processing, layer arithmetic execution processing, and dummy pattern generation processing. When calculating a pattern graphic area, a graphic area calculation part (12) eliminates any overlap between graphics in order to avoid duplicate calculation. Based on the pattern graphic area, a pattern-density data calculation part (13) calculates the area ratios of graphic elements, i.e., pattern elements, contained in a unit region.

Abstract: There are saved layout data which have parent cell information indicative of higher order cell data to directly refer to low order cell data (or basic element data), thereby defining a reverse hierarchical structure. More specifically, both of basic element data (figD1 and figD2) have cell data (cell2) as the parent cell information, all of basic element data (figD3 to figD5) have cell data (cell3) as the parent cell information, the cell data (cell3) have two identical cell data (cell2 and cell2) as the parent cell information, and the cell data (cell2) have three identical cell data (cell3, cell3 and cell3) as the parent cell information.

Abstract: A projection aligner of the present invention, in which ultraviolet light emitted from a lamp housing is split by a fly-eye lens into a large number of point light sources which are independent of one another. Further, in this projection aligner, the light is shaped by an aperture, so that a secondary light source plane is formed. Moreover, after an exposure area is established by a blind, a photomask is illuminated. Thereafter, an image of a light source is formed on a pupillary surface of a projection optical system from light diffracted by the photomask. Furthermore, a wave front aberration is compensated by an aberration eliminating filter placed on the pupillary surface of the optical system of the projection aligner. Then, the image of a circuit pattern is formed on a wafer. Thereby, the influence of the aberration of the optical system is eliminated. Consequently, the high-accuracy transferring of the pattern can be achieved.