Abstract: A digital signal processor comprises a code converter which converts an integer coded in a Binary Two's Complement (BTC) code to an integer coded in a Sign Magnitude Binary (SMB) code and/or a code converter which converts the SMB code to the BTC code. An integer coded in the BTC code and stored in an m-bits register is converted to an integer coded in the SMB code and input to an n-bits register, by an EXCLUSIVE OR processing of the bits with the sign bits and by supplementing a logic "1" in the less significant bit next to the least significant bit of the result of the exclusive OR operation. An integer coded in the SMB code and stored in an n-bits register is converted to an integer coded in the BTC code and input to an m-bits register, by an EXCLUSIVE OR processing of m-1 bits of magnitude bits with a sign bit. The code converters have a relatively simple construction, will not output an incorrect result, and are most suitable for processing AC signals.

Abstract: When transferring data between plural electronic apparatus, the apparatus are composed so as to transfer floating decimal point data possessing the mantissa portion and exponent portion. Therefore, when transferring fixed decimal point data not having such divisions, a vacant time is left in the composition responsible for transfer, and the number of channels of the input/output data is limited unreasonably. To solve such problems, an apparatus it is designed to store, as well as to input and output, the fixed decimal point data also in the exponent portion storage region other than the mantissa portion storage region in the apparatus for storing fixed decimal point data.