Abstract: A peripheral control processor for controlling data communication between a host processor and a peripheral unit in response to command signals applied to the host processor. The peripheral control processor has an idle time or a standby condition when data communication is not required. When the peripheral control processor is idle or in a standby condition, a control circuit, within the processor inhibits a control clock signal which activates transistor elements of an internal circuit in the processor. Therefore, unnecessary power comsumption is reduced during idle time or a standby condition. Further, the control circuit can produce the inhibition signal by using the command signals used for data communication. Therefore, no new signals or terminals are required for applying input signals to the control circuit.