Patents by Inventor Kazuyasu Adachi

Kazuyasu Adachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6479837
    Abstract: A bottom-gate type thin-film transistor free from alignment shift of the gate electrode and from damage caused by injection of impurities. The crystal grains of a polycrystalline silicon thin-film are anisotropically grown to form a prescribed angle relative to the gate length direction. The angle between the gate length direction and the longitudinal direction of the grains is adjusted according to use of the liquid crystal display unit. The bottom-gate transistor includes an undercoat insulating layer containing impurities on the substrate. Impurities are diffused from the undercoat layer to the semiconductor layer by laser-annealing the amorphous silicon.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: November 12, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazufumi Ogawa, Kazuyasu Adachi
  • Patent number: 6472297
    Abstract: There is suggested a method for forming a good-quality polysilicon layer having a large area through a low temperature process even if laser annealing is not conducted. An object of the present invention is therefore to provide a poly-Si TFT array substrate exhibiting little display unevenness and having a high exactitude even if it has a large screen. This object can be attained by a method for producing a TFT array substrate for a liquid crystal display device, comprising a process of forming, on a substrate, a poly-Si TFT in which a polysilicon semiconductor layer is used in a channel area, comprising a polysilicon layer forming step of depositing silicon particles excited by adding energy beforehand onto the substrate so that the polysilicon layer is formed at the stage when the silicon particles are deposited on the substrate.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: October 29, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazufumi Ogawa, Kazuyasu Adachi
  • Patent number: 6342716
    Abstract: A semiconductor device as a nonvolatile memory comprises dot elements which are formed out of the semiconductor or conductor fine particles and function as a floating gate. The dot elements are asymmetrically formed to a control gate and may be formed in a sidewall insulating film formed over the side face of the control gate or a select gate. When inclined or stepped portions having level differences are formed in a semiconductor substrate, the dot elements are formed on a specified portion of the inclined or stepped portions.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: January 29, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoyuki Morita, Kiyoshi Morimoto, Kiyoshi Araki, Koichiro Yuki, Kazuyasu Adachi, Masayuki Endo, Ichiro Yamashita
  • Patent number: 6303516
    Abstract: A Rat IgG antibody film, formed on a p-type Si substrate, is selectively irradiated with ultraviolet rays, thereby leaving part of the Rat IgG antibody film, except for a region deactivated with the ultraviolet rays. Next, when the p-type Si substrate is immersed in a solution containing Au fine particles that have been combined with a Rat IgG antigen, the Rat IgG antigen is selectively combined with the Rat IgG antibody film. As a result, Au fine particles, combined with the Rat IgG antigen, are fixed on the Rat IgG antibody film. Thereafter, the p-type Si substrate is placed within oxygen plasma for 20 minutes, thereby removing the Rat IgG antibody film, the deactivated Rat IgG antibody film and the Rat IgG antigen. Consequently, dot elements can be formed at desired positions on the p-type Si substrate. If these dot elements are used for the floating gate of a semiconductor memory device, then the device has a structure suitable for miniaturization.
    Type: Grant
    Filed: December 10, 1998
    Date of Patent: October 16, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoyuki Morita, Kiyoshi Morimoto, Kiyoshi Araki, Koichiro Yuki, Kazuyasu Adachi, Masayuki Endo, Ichiro Yamashita
  • Patent number: 6127211
    Abstract: In a method of manufacturing a semiconductor device having an LDD structure, source gases for generating plural types of impurity ions exhibiting different molecular weights and different projected ranges in a target during impurity implantation are supplied to a plasma space, ionized, accelerated with a voltage, and implanted in a semiconductor region on the target substrate. In the case of manufacturing a top-gate transistor, a gate electrode on the semiconductor region has a sufficient thickness to serve as a mask. In the case of manufacturing a bottom-gate transistor, a mask and a resistor are used. An implantation angle is set to an optimum value as desired. Thereafter, the impurity is activated as desired. Thus, the semiconductor device having the LDD structure is manufactured by a single step of impurity implantation.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: October 3, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Hirao, Akihisa Yoshida, Toru Fukumoto, Kazuyasu Adachi