Patents by Inventor Kazuyo ISHII

Kazuyo ISHII has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reliability evaluation apparatus
    Patent number: 11158395
    Abstract: A reliability evaluation apparatus according to the present embodiment is provided with a housing and a board insertable into the housing. A plurality of sockets are provided on the board. Semiconductor devices are respectively attachable to socket. The plurality of sockets have electrodes electrically connectable to terminals of the semiconductor devices. A heater is provided inside the housing. A controller is connected to the plurality of sockets and to the heater. The controller controls a voltage to be applied to the terminal of the semiconductor device and controls an output of the heater. A plurality of electromagnets are arranged inside the housing so as to be positioned above or below the plurality of sockets when the board is inserted into the housing.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: October 26, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuyo Ishii, Hiroaki Maekawa
  • RELIABILITY EVALUATION APPARATUS
    Publication number: 20200294613
    Abstract: A reliability evaluation apparatus according to the present embodiment is provided with a housing and a board insertable into the housing. A plurality of sockets are provided on the board. Semiconductor devices are respectively attachable to socket. The plurality of sockets have electrodes electrically connectable to terminals of the semiconductor devices. A heater is provided inside the housing. A controller is connected to the plurality of sockets and to the heater. The controller controls a voltage to be applied to the terminal of the semiconductor device and controls an output of the heater. A plurality of electromagnets are arranged inside the housing so as to be positioned above or below the plurality of sockets when the board is inserted into the housing.
    Type: Application
    Filed: August 30, 2019
    Publication date: September 17, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuyo ISHII, Hiroaki MAEKAWA
  • Semiconductor memory device with correcting resistances in series with memory array signal lines
    Patent number: 10593375
    Abstract: According to one embodiment, a semiconductor storage device comprises a first memory cell including a first resistance change element; a first bit line and a first source line coupled to the first memory cell; and a first resistance coupled to at least one of the first bit line and the first source line.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: March 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kazuyo Ishii
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20190088289
    Abstract: According to one embodiment, a semiconductor storage device comprises a first memory cell including a first resistance change element; a first bit line and a first source line coupled to the first memory cell; and a first resistance coupled to at least one of the first bit line and the first source line.
    Type: Application
    Filed: March 7, 2018
    Publication date: March 21, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Kazuyo ISHII