Patents by Inventor Kazuyo Ohta
Kazuyo Ohta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9791888Abstract: A power reception device in a power transmission system including a power transmission device including a primary coil and the power reception device including a secondary coil, the power transmission device being configured to drive the primary coil and transmit AC power corresponding to a clock signal which is frequency-modulated according to a binary data signal, the primary coil and the secondary coil being electromagnetically coupled together to receive by the secondary coil in the power reception device, the AC power transmitted from the power transmission device, comprises a clock-signal extraction circuit configured to extract the clock signal from an induced voltage induced at one end of the secondary coil in receiving the AC power; and a demodulation circuit configured to generate a pulse synchronously with the clock signal extracted by the clock-signal extraction circuit, and demodulate the pulse to obtain the binary data signal.Type: GrantFiled: October 1, 2012Date of Patent: October 17, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Kazuyo Ohta, Hideyuki Kihara, Yohei Nagatake, Kyohei Kada
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Patent number: 9306400Abstract: A power transmission device in a power transmission system including the power transmission device including a primary coil and a power reception device including a secondary coil, the primary coil being electromagnetically coupled to the secondary coil, to receive in the power reception device AC power transmitted from the power transmission device, comprises a waveform monitor circuit configured to detect an electric potential at one end of the primary coil and output a waveform monitor signal formed by restricting the detected electric potential to an electric potential which is equal to or higher than a ground electric potential; a waveform detection circuit configured to detect a waveform change in the waveform monitor signal input from the waveform monitor circuit; and a data detection circuit configured to detect data transmitted by load change by a load modulation unit in the power reception device based on a result of detection of the waveform change detected by the waveform detection circuit.Type: GrantFiled: September 27, 2012Date of Patent: April 5, 2016Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Hideyuki Kihara, Kazuyo Ohta, Kazuhiro Suzuki, Kyohei Kada, Takaoki Matsumoto
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Patent number: 9252756Abstract: Provided is a random number generating device capable of generating highly irregular random numbers with a simple configuration. The random number generating device includes: a receiving unit including a receiving mechanism configured to receive, in a contactless manner, energy transmitted from a transmitting unit, the receiving unit being configured to convert the energy received by the receiving mechanism into a reception voltage; a voltage controlled oscillator configured to output an oscillating output signal based on the reception voltage; and a pseudorandom number generator configured to generate pseudorandom numbers varying in accordance with an oscillation frequency of the output signal from the voltage controlled oscillator.Type: GrantFiled: September 30, 2013Date of Patent: February 2, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hideyuki Kihara, Kazuyo Ohta
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Publication number: 20140028404Abstract: Provided is a random number generating device capable of generating highly irregular random numbers with a simple configuration. The random number generating device includes: a receiving unit including a receiving mechanism configured to receive, in a contactless manner, energy transmitted from a transmitting unit, the receiving unit being configured to convert the energy received by the receiving mechanism into a reception voltage; a voltage controlled oscillator configured to output an oscillating output signal based on the reception voltage; and a pseudorandom number generator configured to generate pseudorandom numbers varying in accordance with an oscillation frequency of the output signal from the voltage controlled oscillator.Type: ApplicationFiled: September 30, 2013Publication date: January 30, 2014Applicant: PANASONIC CORPORATIONInventors: Hideyuki KIHARA, Kazuyo OHTA
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Publication number: 20120326662Abstract: A contactless power transmitting device is provided with: a primary coil that can be magnetically coupled with a secondary coil of a contactless power receiving device; a first temperature sensor that detects the ambient temperature of the primary coil; a second temperature sensor that detects the temperature at a different location to the first temperature sensor; and a control unit. The control unit is configured to determine whether a value obtained by subtracting the temperature detected by the second temperature sensor from the ambient temperature of the first coil detected by the first temperature sensor exceeds a predetermined threshold value, and to stop the power to the first coil when the subtracted value exceeds the threshold value.Type: ApplicationFiled: March 8, 2011Publication date: December 27, 2012Inventors: Takaoki Matsumoto, Atsushi Isaka, Kazuhiro Suzuki, Kyohei Kada, Yoshihide Kanakubo, Yohei Nagatake, Kazuyo Ohta
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Publication number: 20120313579Abstract: A primary-side controller (12) retains a reference current value corresponding to an input current measured in the previous detection cycle by an input current measurement unit (11), in a charging state. The primary-side controller (12) adds the retained reference current value and a predetermined current value, and generates a first threshold value. When the input current measured by the input current measurement unit (11) in the latest detection cycle is equal to or greater than the first threshold value, a determination is made that a foreign metal is present in the vicinity of a first coil (L1).Type: ApplicationFiled: March 7, 2011Publication date: December 13, 2012Inventors: Takaoki Matsumoto, Atsushi Isaka, Kazuhiro Suzuki, Kyohei Kada, Yoshihide Kanakubo, Yohei Nagatake, Kazuyo Ohta
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Publication number: 20110080198Abstract: A charge pump circuit of the present invention comprises a resistance voltage divider provided between a reference voltage source and an output terminal, a differential amplifier which has an inverting input terminal applied with a divided voltage portion from the resistance voltage divider and a non-inverting input terminal applied with a comparison voltage and is configured to output an output signal obtained by amplifying a potential difference between the divided voltage portion and the comparison voltage through an output terminal, a clock feeder configured to output first and second clock signals according to an original clock signal, and a pump circuit section which is applied with the first and second clock signals alternately and control an output voltage at an output terminal, and the clock feeder is configured to regulate amplitude levels of the first and second clock signals according to the voltage of the output signal.Type: ApplicationFiled: July 26, 2010Publication date: April 7, 2011Inventors: Kazuyo Ohta, Hideyuki Kihara
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Patent number: 7906988Abstract: The tolerant buffer circuit and interface are provided in which reverse inflow of current to a power supply voltage from an output terminal does not occur, even if the output terminal is at a higher potential than an output circuit power supply voltage during open-drain operation in an output circuit of a semiconductor integrated circuit, or if the output circuit power supply voltage becomes 0 V.Type: GrantFiled: November 19, 2009Date of Patent: March 15, 2011Assignee: Panasonic CorporationInventors: Kazuyo Ohta, Hideyuki Kihara
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Publication number: 20100134147Abstract: A tolerant buffer circuit and interface are provided in which reverse inflow of current to a power supply voltage from an output terminal does not occur even if the output terminal is at a higher potential than an output circuit power supply voltage during open-drain operation in an output circuit of a semiconductor integrated circuit, or if the output circuit power supply voltage becomes 0 V. Tolerant buffer circuit 100 is provided with PMOS transistors Q111 and Q112 that are connected in series and that share a source between power supply terminal VDD1 and output terminal 102, NMOS transistor Q113 connected between output terminal 102 and ground terminal 101, inverter 121 output-connected to the gate of PMOS transistor Q111, inverter 122 output-connected to the gate of PMOS transistor Q112, and control circuit 130 that outputs first, second, and third control signals to PMOS transistor Q111, PMOS transistor Q112, and NMOS transistor Q113 respectively, and controls the on/off state of these MOS transistors.Type: ApplicationFiled: November 19, 2009Publication date: June 3, 2010Applicant: PANASONIC CORPORATIONInventors: Kazuyo OHTA, Hideyuki KIHARA
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Publication number: 20040137413Abstract: There are intellectual evaluation devices in which interview content is previously registered by a doctor, its answers are managed electronically, and intellectual activity is evaluated for preventing the decline of mental activity such as dementia. However, with such conventional intellectual evaluation devices, the declining degree of intellectual activity of the user could not be monitored properly, for example, for the reasons that the subject feels resistance to being subjected to judgment evaluation, and the like.Type: ApplicationFiled: February 23, 2004Publication date: July 15, 2004Inventors: Hiroshi Yamamoto, Kazuyo Ohta
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Patent number: 4661588Abstract: Compounds of the formula ##STR1## wherein R.sub.1 is lower alkyl, lower alkoxycarbonyl-lower alkyl, phenyl, phenyl substituted by one or more lower alkyl or halogen, phenyl-lower alkyl optionally substituted in its side chain by lower alkyl or lower alkoxycarbonyl, thienylmethyl or thiazolyl, R.sub.2 is hydrogen or lower alkyl, or ##STR2## constitutes a 3-7-membered nitrogen-containing heterocyclic ring in which R.sub.1 and R.sub.2 are connected, R.sub.3 is hydrogen or hydroxyl, and X is oxygen or sulfur, or a non-toxic salt thereof. These compounds have stronger antibacterial activity as compared with known clinically used macrolide antibiotics such as erythromycin, oleandomycin, josamycin and leucomycin, and also have strong antibacterial activity against all macrolide antibiotic-resistant strains such as macrolide-resistant A group strains (clinical isolates or erythromycin, oleandomycin and 16-membered macrolide antibiotic resistant strains).Type: GrantFiled: October 25, 1985Date of Patent: April 28, 1987Assignee: Toyo Jozo Kabushiki KaishaInventors: Tatsuro Fujiwara, Kazuyo Ohta, Eiichi Honda, Takao Hirano, Hideo Sakakibara
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Patent number: 4652638Abstract: Novel 3-O-acyl-4"-deoxydesmycosin derivatives of the formula ##STR1## wherein R.sub.1 is lower alkyl, phenyl, substituted phenyl, phenyl-lower alkyl or substituted phenyl-lower alkyl, R.sub.2 is hydrogen or --CHO and R.sub.3 is hydrogen or hydroxyl, or a non-toxic salt thereof, can be produced by acylating the hydroxyl group at position-3 of the corresponding intermediate while protecting the hydroxyl at position-2' or positions-2' and -4' with acetyl, and then removing the protective group or groups. These derivatives have antibiotic utility against Gram positive and Gram negative bacteria.Type: GrantFiled: September 30, 1985Date of Patent: March 24, 1987Assignee: Toyo Jozo Kabushiki KaishaInventors: Tatsuro Fujiwara, Kazuyo Ohta, Takao Hirano