Abstract: Disclosed is a semiconductor apparatus adapted to reduce the inflow of current from an external input terminal in a power saving mode. A mode decision circuit 11 outputs to an interruption circuit 10 and a floating prohibiting circuit 15 a mode signal indicating whether operation of the semiconductor apparatus is power saving mode or regular operating mode. When the mode signal indicates the power saving mode, the interruption circuit 10 is rendered non-conductive to disconnect an external input terminal 13 on one hand and an input capacitance adjustment capacitor 12 and an initial stage input circuit 14 on the other hand from each other. The floating prohibiting circuit 15 also sets the voltage at an input end of the initial stage input circuit 14 at a preset voltage level.

Abstract: Disclosed is a semiconductor apparatus adapted to reduce the inflow of current from an external input terminal in a power saving mode. A mode decision circuit 11 outputs to an interruption circuit 10 and a floating prohibiting circuit 15 a mode signal indicating whether operation of the semiconductor apparatus is power saving mode or regular operating mode. When the mode signal indicates the power saving mode, the interruption circuit 10 is rendered non-conductive to disconnect an external input terminal 13 on one hand and an input capacitance adjustment capacitor 12 and an initial stage input circuit 14 on the other hand from each other. The floating prohibiting circuit 15 also sets the voltage at an input end of the initial stage input circuit 14 at a preset voltage level.

Abstract: A dynamic memory circuit provided with an improved bit line reference voltage control circuit realized by a small capacitance of an adjustment capacitor is disclosed. The memory circuit includes a short-circuiting circuit for setting each pair of bit lines at an intermediate voltage of a power source voltage, a capacitor for lowering the intermediate voltage according to charge division based on a ration of a capacitance of the adjustment capacitor and a total capacitance of the bit lines, and a boot-strap circuit for operatively causing a level reduction more than the power source voltage in the capacitor.