Abstract: An ultrasonic probe includes, a transducer transmitting and receiving ultrasonic waves, and converting ultrasonic signals into voltage signals and vice versa, a first circuit configured to transmit pulse voltage signals to the transducer and receive the voltage signals from the transducer, a second circuit configured to convert the voltage signals received from the first circuit into digital values from analog values, a battery unit configured to supply electric power to the first circuit and the second circuit, and a substrate being provided with the transducer, the first circuit and the second circuit, the first circuit being disposed on a first surface of the substrate, and the second circuit being disposed on a second surface opposite to the first surface of the substrate.

Abstract: An ultrasonic probe includes, a transducer transmitting and receiving ultrasonic waves, and converting ultrasonic signals into voltage signals and vice versa, a first circuit configured to transmit pulse voltage signals to the transducer and receive the voltage signals from the transducer, a second circuit configured to convert the voltage signals received from the first circuit into digital values from analog values, a battery unit configured to supply electric power to the first circuit and the second circuit, and a substrate being provided with the transducer, the first circuit and the second circuit, the first circuit being disposed on a first surface of the substrate, and the second circuit being disposed on a second surface opposite to the first surface of the substrate.

Abstract: A synchronization determination method includes: a synchronization determining step of determining whether or not synchronization has been successfully performed by detecting a synchronous pattern from the demodulated data input as a data stream; a synchronization probability determining step of determining whether or not there is a probability that synchronization is successfully performed using the progress of detecting a synchronous pattern in the synchronization determining step; and a synchronization determination discard step of discarding a determination in the synchronization determining step when it is determined in the synchronization probability determining step that there is no probability that synchronization is successfully performed, and passing control to the process performed when it is determined in the synchronization determining step that synchronization has not been successfully performed.

Abstract: A data input circuit converts input serial data to n-bit parallel data, and outputs the n-bit parallel data by following an address signal. The data input circuit includes a data shifting unit including a plurality of columns, and sequentially shifting the input serial data through the plurality of columns; and a selection unit selecting a column among the plurality of columns as an input column by following the address signal, wherein the input serial data is inputted to the data shifting unit through the input column. Thus, the data input device can speed up its processing speed with a simplified circuit structure whose circuit size is reduced.

Abstract: A synchronizing apparatus comprises a normal lock synchronization detecting unit for detecting synchronization by detecting from demodulated data a synchronization pattern in a normal lock state, and a pseudo lock synchronization detecting unit for detecting synchronization by detecting from the demodulated data a synchronization pattern in a pseudo lock state.

Abstract: A synchronizing apparatus comprises a normal lock synchronization detecting unit for detecting synchronization by detecting from demodulated data a synchronization pattern in a normal lock state, and a pseudo lock synchronization detecting unit for detecting synchronization by detecting from the demodulated data a synchronization pattern in a pseudo lock state.

Abstract: A synchronization determination method includes: a synchronization determining step of determining whether or not synchronization has been successfully performed by detecting a synchronous pattern from the demodulated data input as a data stream; a synchronization probability determining step of determining whether or not there is a probability that synchronization is successfully performed using the progress of detecting a synchronous pattern in the synchronization determining step; and a synchronization determination discard step of discarding a determination in the synchronization determining step when it is determined in the synchronization probability determining step that there is no probability that synchronization is successfully performed, and passing control to the process performed when it is determined in the synchronization determining step that synchronization has not been successfully performed.

Abstract: A timing recovery circuit includes a first oscillating circuit configured to produce a first timing signal, a second oscillating circuit configured to produce a second timing signal, a first decimation circuit coupled to a supply node of a first clock signal and to the first oscillating circuit to produce a second clock signal made by decimating pulses of the first clock signal in response to the first timing signal, and a second decimation circuit coupled to the first decimation circuit and to the second oscillating circuit to produce a third clock signal made by decimating pulses of the second clock signal in response to the second timing signal, wherein one of the first timing signal and the second timing signal has a fixed cycle, and another one has a cycle responsive to feedback control.

Abstract: A data input circuit converts input serial data to n-bit parallel data, and outputs the n-bit parallel data by following an address signal. The data input circuit includes a data shifting unit including a plurality of columns, and sequentially shifting the input serial data through the plurality of columns; and a selection unit selecting a column among the plurality of columns as an input column by following the address signal, wherein the input serial data is inputted to the data shifting unit through the input column. Thus, the data input device can speed up its processing speed with a simplified circuit structure whose circuit size is reduced.

Abstract: A data input circuit converts input serial data to n-bit parallel data, and outputs the n-bit parallel data by following an address signal. The data input circuit includes a data shifting unit including a plurality of columns, and sequentially shifting the input serial data through the plurality of columns; and a selection unit selecting a column among the plurality of columns as an input column by following the address signal, wherein the input serial data is inputted to the data shifting unit through the input column. Thus, the data input device can speed up its processing speed with a simplified circuit structure whose circuit size is reduced.

Abstract: A timing recovery circuit includes a first oscillating circuit configured to produce a first timing signal, a second oscillating circuit configured to produce a second timing signal, a first decimation circuit coupled to a supply node of a first clock signal and to the first oscillating circuit to produce a second clock signal made by decimating pulses of the first clock signal in response to the first timing signal, and a second decimation circuit coupled to the first decimation circuit and to the second oscillating circuit to produce a third clock signal made by decimating pulses of the second clock signal in response to the second timing signal, wherein one of the first timing signal and the second timing signal has a fixed cycle, and another one has a cycle responsive to feedback control.

Abstract: Disclosed is a transmitter apparatus which creates a PI frame (Pause-In frame) and a PO frame (Pause-Out frame) and transmits each frame to a router for executing flow control. When creation of a PI frame is commanded from a band controller, or when a flow-control start request is detected from a signal that enters from a transmission line, the transmitter apparatus sends a PI frame to a router to allow execution of flow control. When creation of a PO frame is commanded from the band controller and, moreover, a flow-control halt request is detected from a signal that enters from the transmission line at such time that the router is performing flow control, the transmitting apparatus creates the PO frame and sends it to the router to halt flow control.

Abstract: A semiconductor memory device having an internal circuit includes a command decoder which decodes input-command signals to supply decoded-command signals, an address-latch-signal-generation circuit, operating faster than the command decoder, which decodes the input-command signals to supply an address-latch signal, and a control circuit which controls the internal circuit based on the decoded-command signals. The semiconductor memory device further includes an address-input circuit which latches an address signal in response to the address-latch signal.

Abstract: Disclosed is a transmitter apparatus which creates a PI frame (Pause-In frame) and a PO frame (Pause-Out frame) and transmits each frame to a router for executing flow control. When creation of a PI frame is commanded from a band controller, or when a flow-control start request is detected from a signal that enters from a transmission line, the transmitter apparatus sends a PI frame to a router to allow execution of flow control. When creation of a PO frame is commanded from the band controller and, moreover, a flow-control halt request is detected from a signal that enters from the transmission line at such time that the router is performing flow control, the transmitting apparatus creates the PO frame and sends it to the router to halt flow control.

Abstract: The semiconductor integrated circuit comprises a parallel-serial converter for converting parallel data read from memory cells into serial data and a switch control circuit for receiving a control signal and controlling the parallel-serial converter. The parallel-serial converter has a plurality of switches connected in a predetermined order. The switch control circuit controls the order of connecting the switches in accordance with the control signal so that parallel data are converted into serial data in a predetermined bit order. This minimizes delay elements formed on the transmission paths of parallel data. Specifically, for example, it eliminates the need for a conversion circuit for changing the bit order of parallel data. This results in faster data read operations from memory cells. Each of the switches in the parallel-serial converter operates in synchronization with a clock signal supplied from the exterior.

Abstract: The address holding part holds a write address supplied corresponding to a write command, as a held write address. The data holding part writes a held write data to a memory cell corresponding to the held write address when receiving the next write command. The address comparison part has a plurality of address comparators that compare a read address, with a held write address, by a plurality of bits. When the results of comparison of the address comparison part are coincident in a read operation, the held write data are outputted as read data. Since the read address and the held write address are compared by a plurality of address comparators, the scale of circuits in the address comparison part can be reduced. Moreover, the addresses can be compared at a high rate, so that the read operation can be performed at a high rate.