Abstract: A constant voltage circuit adapted for connection between high voltage power source and low voltage power source terminals respectively to output a constant voltage signal from an output terminal in response to a control signal inputted to an input terminal. The circuit has a resistor circuit including a MOS transistor for connection to the high voltage power source and activated in response to the control signal. A current mirror section is connected between the resistor circuit and the low voltage power source terminal to generate an output voltage to be outputted from the output terminal. A feedback section is connected between the resistor circuit and the low voltage power source terminal to control the current mirror section to keep the output voltage constant by detecting deviation of the output voltage.

Abstract: A level conversion circuit includes an ECL logic circuit including a current switch circuit having first and second transistors, each of the transistors having an emitter coupled to each other and at least one thereof receiving an input signal of ECL logic level, and an output transistor coupled to a collector of at least one of the first and second transistors; a current control circuit including a current mirror circuit having third and fourth transistors, at least one of the transistors being coupled to an output end of the output transistor, and controlling a current flowing through the output to thereby carry out a level conversion of a signal at the output end; and a switch circuit operative coupled to the current control circuit. The switch circuit responds to a control signal and thus controls a supply of a current or a break thereof from the output transistor to the current control circuit.

Abstract: A bias voltage generation circuit comprises a bias voltage generation portion having a bias control node, a first switching unit, and a second switching unit. The bias voltage generation portion is used to generate a bias voltage of a predetermined potential and supply the bias voltage to an ECL circuit during an operation period, and the first switching unit is used to drop the bias voltage during a standby period in response to a bias voltage control signal. The second switching unit is used to switch OFF during the standby period to cut off a current flow through the bias control node and switch ON during the operation period to supply a current through the bias control node in response to the bias voltage control signal. Consequently, a current flow during the standby period can be reduced, and power consumption of the bias voltage generation circuit during the standby period is minimal.

Abstract: A PLL synthesizer includes a voltage-controlled oscillator generating an output signal having a frequency based on a first signal supplied thereto, a PLL control circuit which generates a second signal based on the output signal and a set frequency, a lowpass filter having an input terminal and an output terminal, for filtering the second signal supplied through the input terminal to thereby generate the first signal supplied to the voltage-controlled oscillator through the output terminal, and a switch circuit which is coupled between the input and output terminals of the lowpass filter and which supplies the second signal directly to the voltage-controlled oscillator during a predetermined time when the set frequency is changed.

Abstract: A semiconductor integrated circuit includes a logic circuit which has first and second transistors constituting an emitter coupled transistor pair and a third transistor which is used as a constant current source, a bias circuit which includes a fourth transistor having an emitter from which a first predetermined voltage is supplied to a base of the third transistor and an impedance having one end coupled to a first power source and another end coupled to a base of the fourth transistor to supply a second predetermined voltage thereto, and a clamping circuit. The clamping circuit is OFF and does not perform a clamping operation with respect to the base of the fourth transistor when the entire semiconductor integrated circuit needs to operate. When the entire semiconductor integrated circuit does not need to operate, the clamping circuit is ON to clamp the base potential of the fourth transistor so as to reduce the power consumption of the semiconductor integrate circuit.