Abstract: A current summing type D/A converter having a configuration of two or more steps is provided. In a D/A converter block of the first step, by adding current segments, upper bits are D/A converted, and one of the current segments in the first step is further supplied to a D/A converter block in a second step to be shunt by the D/A converter block in the second step, so that lower bits are D/A converted. The output current in the first step and the output current in the second step are then added each other. According to the foregoing method, the D/A conversion may be performed without causing a differential linearity error.

Abstract: A current summing type D/A converter having a configuration of two or more steps is provided. In a D/A converter block of the first step, by adding current segments, upper bits are D/A converted, and one of the current segments in the first step is further supplied to a D/A converter block in a second step to be shunt by the D/A converter block in the second step, so that lower bits are D/A converted. The output current in the first step and the output current in the second step are then added each other. According to the foregoing method, the D/A conversion may be performed without causing a differential linearity error.

Abstract: A device for measuring temperature of a semiconductor integrated circuit includes first and second current mirror circuits, an N channel transistor connected to an output terminal of the second cur rent mirror circuit, an npn transistor connected to an output terminal of the first current mirror circuit and the N channel transistor, and an operational transistor connected to a node between the second current circuit and the N channel transistor. Currents that flow from the second current mirror circuit to the N channel transistor and from the N channel transistor to the npn transistor have different temperature coefficients. The operational amplifier corrects the difference in the temperature coefficients of these currents to output a voltage of ground electric potential standard.

Abstract: Includes first and second current mirror circuits, an N channel transistor connected to an output terminal of the second current mirror circuit, an npn transistor connected to an output terminal of the first current mirror circuit and the N channel transistor, and an operational transistor connected to a node between the second current circuit and the N channel transistor. Current that flow from the second current mirror circuit to the N channel transistor and from the N channel transistor to the npn transistor have different temperature coefficients. The operational amplifier corrects the difference in the temperature coefficients of these currents to output a voltage of ground electric potential standard.

Abstract: A non-volatile semiconductor memory device and a manufacturing method of the same where an etching residue generating short-circuit between gates is made harmless or a device is miniaturized are obtained. The method includes the steps of forming on a semiconductor substrate, a first gate layer and a second gate layer, forming a second gate electrode by etching the second gate layer, forming a first gate electrode by etching the first gate layer using the second gate electrode as a mask, and removing a residue left on a step portion by isotropic etching.

Abstract: There is described formation of a contact hole without involvement of damage to an etching stopper film and deterioration of electric characteristics, achieved by means of a self-alignment method. An interlayer oxide film is etched through an opening of a resist mask, and by means of plasma etching through use of a processing gas comprising a mixture of a rare gas and a CF-based gas, thereby tapering a shoulder of the silicon nitride film. Alternatively, a silicon oxide film and a silicon nitride film are continually etched through an opening of the resist mask, by means of plasma etching through use of a CH2F2 gas added to a mixed gas including a rare gas and a C4F8 gas.

Abstract: There is described formation of a contact hole without involvement of damage to an etching stopper film and deterioration of electric characteristics, achieved by means of a self-alignment method. An interlayer oxide film is etched through an opening of a resist mask, and by means of plasma etching through use of a processing gas comprising a mixture of a rare gas and a CF-based gas, thereby tapering a shoulder of the silicon nitride film. Alternatively, a silicon oxide film and a silicon nitride film are continually etched through an opening of the resist mask, by means of plasma etching through use of a CH2F2 gas added to a mixed gas including a rare gas and a C4F8 gas.

Abstract: A non-volatile semiconductor memory device and a manufacturing method of the same where an etching residue generating short-circuit between gates is made harmless or a device is miniaturized are obtained. The method includes the steps of forming on a semiconductor substrate, a first gate layer and a second gate layer, forming a second gate electrode by etching the second gate layer, forming a first gate electrode by etching the first gate layer using the second gate electrode as a mask, and removing a residue left on a step portion by isotropic etching.

Abstract: A gate electrode includes a polycrystalline silicon layer, a barrier layer and a metal layer. The metal layer and barrier layer includes for example W and RuO2 layers, respectively. In forming the gate electrode, the metal layer and barrier layer are etched using at least one of the barrier layer and polycrystalline silicon layer as an etching stopper.

Abstract: A non-volatile semiconductor memory device and a manufacturing method of the same where an etching residue generating short-circuit between gates is made harmless or a device is miniaturized are obtained. The method includes the steps of forming on a semiconductor substrate, a first gate layer and a second gate layer, forming a second gate electrode by etching the second gate layer, forming a first gate electrode by etching the first gate layer using the second gate electrode as a mask, and removing a residue left on a step portion by isotropic etching.