Patents by Inventor Kazuyuki Tsunokuni

Kazuyuki Tsunokuni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220123358
    Abstract: A technique of improving the performance of a secondary battery is provided. A secondary battery according to an embodiment includes a first electrode, a second electrode, a first layer disposed on the first electrode and including a first n-type oxide semiconductor, a second layer disposed on the first layer and including a second n-type oxide semiconductor material and a first insulating material, a third layer which is disposed on the second layer and is a solid electrolyte layer, and a fourth layer disposed on the third layer and including hexagonal Ni(OH)2 microcrystals.
    Type: Application
    Filed: January 30, 2020
    Publication date: April 21, 2022
    Inventors: Kazuyuki TSUNOKUNI, Juri OGASAWARA, Takashi TONOKAWA, Hiroyuki KATO
  • Patent number: 11245113
    Abstract: A secondary battery includes: a first oxide semiconductor having a first conductivity type; a first charging layer disposed on the first oxide semiconductor layer, and composed by including a first insulating material and a second oxide semiconductor having the first conductivity type; a second charging layer disposed on the first charging layer; a third oxide semiconductor layer having a second conductivity type disposed on the second charging layer; and a hydroxide layer disposed between the first charging layer and the third oxide semiconductor layer, and containing a hydroxide of a metal constituting the third oxide semiconductor layer. The highly reliable secondary battery is capable of improving an energy density and increasing battery characteristics (electricity accumulation capacity).
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: February 8, 2022
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Takashi Tonokawa, Yutaka Kosaka, Kazuyuki Tsunokuni, Hikaru Takano, Shigefusa Chichibu, Kazunobu Kojima
  • Publication number: 20210351412
    Abstract: A secondary battery includes: a solid electrolyte layer which contains a tantalum oxide as a solid electrolyte; a positive-electrode active material layer which is disposed on an upper surface of the solid electrolyte layer and contains a nickel hydroxide (Ni(OH)2) as a positive-electrode active material; and a negative-electrode active material layer disposed on a lower surface of the solid electrolyte layer so as to be opposite to the positive-electrode active material layer and containing a titanium oxide (TiOx) or a titanium oxide (TiOx) and a silicon oxide (SiOx) as a negative-electrode active material. There is provided a secondary battery capable of improving electricity storage performance by improving a self-discharge.
    Type: Application
    Filed: July 23, 2021
    Publication date: November 11, 2021
    Inventors: Daisuke HASEGAWA, Kazuyuki TSUNOKUNI, Tomokazu SAITO, Taku HIGUTI
  • Publication number: 20210193924
    Abstract: An object of the present invention is to provide a power storage device structure in which the number of layers to be laminated is reduced as compared with a conventional power storage device. A power storage device according to the present invention includes a conductive electrode, an insulator and an n-type metal oxide semiconductor, and a charging layer for storing charges and an iridium oxide layer formed of iridium oxide as a material to be used for a dielectric layer of a solid-state electrochromic element are sequentially laminated. Since iridium oxide has a low resistivity, the iridium oxide layer is given the function of the conductive electrode to eliminate the conductive electrode and reduce the number of layers to be laminated.
    Type: Application
    Filed: April 24, 2018
    Publication date: June 24, 2021
    Inventors: Takuo KUDOH, Kazuyuki TSUNOKUNI
  • Publication number: 20210091400
    Abstract: To provide a manufacturing method of a secondary battery capable of increasing discharge capacity.
    Type: Application
    Filed: December 4, 2020
    Publication date: March 25, 2021
    Applicant: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Kazuyuki TSUNOKUNI, Tomokazu SAITO, Yuki SATO, Hikaru TAKANO
  • Publication number: 20200373575
    Abstract: A secondary battery includes: a solid electrolyte layer including at least one of water (H2O) and a hydroxyl group (—OH); a positive-electrode active material layer disposed on the solid electrolyte layer and including nickel hydroxide; a second electrode (positive electrode) disposed on the positive-electrode active material layer; a negative-electrode active material layer disposed on a lower surface of the solid electrolyte layer so as to be opposite to the positive-electrode active material layer, and including a titanium oxide compound (TiOx) including at least one of water and a hydroxyl group; a first electrode (negative electrode) disposed on a lower surface of the negative-electrode active material layer so as to be opposite to the second electrode; a p type semiconductor layer disposed between the positive-electrode active material layer and the second electrode; and an n type semiconductor layer disposed between the negative-electrode active material layer and the first electrode.
    Type: Application
    Filed: August 12, 2020
    Publication date: November 26, 2020
    Inventors: Kazuyuki TSUNOKUNI, Takashi TONOKAWA, Kunihiko NAKADA, Yutaka KOSAKA
  • Patent number: 10705151
    Abstract: An intermediate structure unit for a secondary cell according to the present invention is the intermediate structure unit for a secondary cell having a secondary cell and a test structure unit on a common substrate. Each of the secondary cell and the test structure unit includes a first electrode layer and a second electrode layer. A plurality of layers are layered at the secondary cell between the first electrode layer and the second electrode layer. The plurality of layers include at least a metal oxide semiconductor layer and a charging layer. A party of the plurality of layers is formed at the test structure unit between the first electrode layer and the second electrode layer.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: July 7, 2020
    Assignee: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Yuki Sato, Kazuyuki Tsunokuni, Tomokazu Saito
  • Patent number: 10686210
    Abstract: A method for manufacturing oxide semiconductor secondary cells concurrently and evenly on a plurality of chips. A method for manufacturing a chip on which an oxide semiconductor secondary cell is mounted, the oxide semiconductor secondary cell that is formed by layering a first electrode, a charging function layer, and a second electrode being layered on a circuit. The method includes a layering process to layer and form the oxide semiconductor secondary cells integrally at regions corresponding to a plurality of chips formed on a wafer without separately forming oxide semiconductor secondary cells at regions corresponding to the respective chips, and a separating process to perform separation into individual oxide semiconductor secondary cells corresponding to the respective chips by performing pattern etching on the integrally-formed oxide semiconductor secondary cells to eliminate regions not corresponding to the respective chips except for regions corresponding to the respective chips.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: June 16, 2020
    Assignee: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Kazuyuki Tsunokuni, Tatsuo Inoue, Tomokazu Saitoh, Juri Ogasawara, Takashi Tonokawa, Takuo Kudoh
  • Publication number: 20200006763
    Abstract: The electricity storage device includes: a first oxide semiconductor layer having a first conductivity-type first oxide semiconductor; a first charge layer disposed on the first oxide semiconductor layer, and composed by including a first insulating material and a first conductivity-type second oxide semiconductor; and a third oxide semiconductor layer disposed on the first charge layer. The third oxide semiconductor layer has hydrogen and a second conductivity-type third oxide semiconductor, and a percentage of the hydrogen with respect to a metal constituting the third oxide semiconductor is equal to or greater than 40%. The embodiments provide an electricity storage device capable of increasing an electricity storage capacity per unit volume (weight).
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Inventors: Takashi TONOKAWA, Kazuyuki TSUNOKUNI, Takuo KUDOH
  • Publication number: 20200006009
    Abstract: The electricity storage device includes: a first conductivity-type first oxide semiconductor; a solid electrolyte layer disposed on the first oxide semiconductor layer, the solid electrolyte layer including a solid electrolyte enabling proton movement; an insulator layer disposed between the solid electrolyte layer and the first oxide semiconductor layer, the insulator layer including an insulating material; and a second conductivity-type second oxide semiconductor layer disposed on the solid electrolyte layer. Provided is the electricity storage device having the increased electricity storage capacity and improved reliability that can be charged without degradation even when the charging voltage is increased.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Inventors: Takashi TONOKAWA, Kazuyuki TSUNOKUNI, Juri OGASAWARA, Yuki SATO
  • Publication number: 20200006764
    Abstract: A secondary battery includes: a first conductivity-type first oxide semiconductor; a first charge layer disposed on the first oxide semiconductor layer, the first charge layer composed by including a first metal oxide; a first separation layer disposed on the first charge layer; and a second conductivity-type second oxide semiconductor layer disposed on the first separation layer. The first charge layer is not composed of a material containing silicon. A second separation layer disposed on the first charge layer between the first separation layer and the first charge layer may be included. Provided is a secondary battery capable of reducing an internal resistance and capable of increasing an electricity storage capacity per unit volume (weight).
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Inventors: Tomokazu SAITO, Hikaru TAKANO, Yuki SATO, Kazuyuki TSUNOKUNI
  • Publication number: 20190273278
    Abstract: A method of manufacturing a secondary battery includes a first electrode, an n-type metal oxide semiconductor layer made of an n-type metal oxide semiconductor, an n-type metal oxide semiconductor and an insulator, an intermediate insulating layer containing an insulator as a main component, a p-type metal oxide semiconductor layer made of a p-type metal oxide semiconductor, and a second electrode are laminated in this order, a first process of applying a positive voltage between the first electrode and the second electrode with reference to the first electrode and a second process of applying a positive voltage between the first electrode and the second electrode, and a second process in which 0 V is applied between the first process cycle and the second process cycle in this order is defined as a first unit cycle and a predetermined number of first unit cycles are repeated.
    Type: Application
    Filed: April 4, 2017
    Publication date: September 5, 2019
    Applicant: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Kazuyuki TSUNOKUNI, Tomokazu SAITO, Yuki SATO, Hikaru TAKANO
  • Publication number: 20190190024
    Abstract: A secondary battery includes: a first oxide semiconductor having a first conductivity type; a first charging layer disposed on the first oxide semiconductor layer, and composed by including a first insulating material and a second oxide semiconductor having the first conductivity type; a second charging layer disposed on the first charging layer; a third oxide semiconductor layer having a second conductivity type disposed on the second charging layer; and a hydroxide layer disposed between the first charging layer and the third oxide semiconductor layer, and containing a hydroxide of a metal constituting the third oxide semiconductor layer. The highly reliable secondary battery is capable of improving an energy density and increasing battery characteristics (electricity accumulation capacity).
    Type: Application
    Filed: February 26, 2019
    Publication date: June 20, 2019
    Inventors: Takashi TONOKAWA, Yutaka KOSAKA, Kazuyuki TSUNOKUNI, Hikaru TAKANO, Shigefusa CHICHIBU, Kazunobu KOJIMA
  • Patent number: 10090507
    Abstract: A secondary battery-mounted circuit chip wherein secondary battery is directly fabricated on opposed surface of formed circuit into an integrated structure of the secondary battery and circuit, and a manufacturing method thereof. Secondary battery-mounted circuit chip is configured such that secondary battery is directly fabricated in region corresponding to circuit into integrated structure of secondary battery and circuit. The chip is secondary battery-mounted circuit chip wherein secondary battery is formed on surface opposing a circuit region fabricated on wafer.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: October 2, 2018
    Assignees: KABUSHIKI KAISHA NIHON MICRONICS, GUALA TECHNOLOGY CO., LTD.
    Inventors: Kazuyuki Tsunokuni, Tatsuo Inoue, Kiyoyasu Hiwada, Takashi Tonokawa, Akira Nakazawa
  • Publication number: 20180226674
    Abstract: A method for manufacturing oxide semiconductor secondary cells concurrently and evenly on a plurality of chips. A method for manufacturing a chip on which an oxide semiconductor secondary cell is mounted, the oxide semiconductor secondary cell that is formed by layering a first electrode, a charging function layer, and a second electrode being layered on a circuit. The method includes a layering process to layer and form the oxide semiconductor secondary cells integrally at regions corresponding to a plurality of chips formed on a wafer without separately forming oxide semiconductor secondary cells at regions corresponding to the respective chips, and a separating process to perform separation into individual oxide semiconductor secondary cells corresponding to the respective chips by performing pattern etching on the integrally-formed oxide semiconductor secondary cells to eliminate regions not corresponding to the respective chips except for regions corresponding to the respective chips.
    Type: Application
    Filed: June 20, 2016
    Publication date: August 9, 2018
    Applicant: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Kazuyuki TSUNOKUNI, Tatsuo INOUE, Tomokazu SAITOH, Juri OGASAWARA, Takashi TONOKAWA, Takuo KUDOH
  • Publication number: 20180210033
    Abstract: An intermediate structure unit for a secondary cell according to the present invention is the intermediate structure unit for a secondary cell having a secondary cell and a test structure unit on a common substrate. Each of the secondary cell and the test structure unit includes a first electrode layer and a second electrode layer. A plurality of layers are layered at the secondary cell between the first electrode layer and the second electrode layer. The plurality of layers include at least a metal oxide semiconductor layer and a charging layer. A party of the plurality of layers is formed at the test structure unit between the first electrode layer and the second electrode layer.
    Type: Application
    Filed: June 23, 2016
    Publication date: July 26, 2018
    Inventors: Yuki SATO, Kazuyuki TSUNOKUNI, Tomokazu SAITO
  • Patent number: 9735594
    Abstract: A charging/discharging device performs charging and discharging on a plurality of secondary cells concurrently in parallel, without adopting a power source having an extremely high current supply capacity. A plurality of switching units controlled by a switching control unit are interposed respectively between the secondary cells and each of a plurality of charging power lines and discharging power lines. A power unit applies voltages having mutually-different voltage values and the switching control unit controls switching so that the respective secondary cells are connected cyclically in predetermined order to the charging and discharge power lines.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: August 15, 2017
    Assignees: KABUSHIKI KAISHA NIHON MICRONICS, GUALA TECHNOLOGY CO., LTD.
    Inventors: Harutada Dewa, Kiyoyasu Hiwada, Tomokazu Saito, Kazuyuki Tsunokuni, Akira Nakazawa
  • Publication number: 20170131361
    Abstract: Handling to a subsequent step of cell examining/testing can be performed as keeping the same shape owing to that a sheet-shaped cell is alternately folded and an electrode terminal is inserted to a gap of the folded sheet-shaped cell, and test space can be saved by lessening a size of a testing device for a cell. A testing device for a sheet-shaped cell and a testing method for a sheet-shaped cell according to the present invention includes a folding unit that folds a sheet-shaped cell having electrode layers on both faces while alternately changing a folding direction, and a testing unit that performs a predetermined test as supplying power to electrode terminals in a state that the electrode terminals are inserted respectively to folded portions of the sheet-shaped cell.
    Type: Application
    Filed: July 31, 2014
    Publication date: May 11, 2017
    Inventors: Tomokazu SAITO, Kazuyuki TSUNOKUNI, Kiyoyasu HIWADA
  • Publication number: 20160181588
    Abstract: A secondary battery-mounted circuit chip wherein secondary battery is directly fabricated on opposed surface of formed circuit into an integrated structure of the secondary battery and circuit, and a manufacturing method thereof. Secondary battery-mounted circuit chip is configured such that secondary battery is directly fabricated in region corresponding to circuit into integrated structure of secondary battery and circuit. The chip is secondary battery-mounted circuit chip wherein secondary battery is formed on surface opposing a circuit region fabricated on wafer.
    Type: Application
    Filed: March 5, 2014
    Publication date: June 23, 2016
    Inventors: Kazuyuki TSUNOKUNI, Tatsuo INOUE, Kiyoyasu HIWADA, Takashi TONOKAWA, Akira NAKAZAWA
  • Publication number: 20150188337
    Abstract: To provide a charging/discharging device capable of performing charging and discharging on a plurality of secondary cells concurrently in parallel without adopting a power source having an extremely high current supply capacity.
    Type: Application
    Filed: July 23, 2013
    Publication date: July 2, 2015
    Inventors: Harutada Dewa, Kiyoyasu Hiwada, Tomokazu Saito, Kazuyuki Tsunokuni, Akira Nakazawa