Patents by Inventor Kazuyuki Umezu
Kazuyuki Umezu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11114527Abstract: A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.Type: GrantFiled: March 11, 2020Date of Patent: September 7, 2021Assignee: Renesas Electronics CorporationInventors: Makoto Koshimizu, Hideki Niwayama, Kazuyuki Umezu, Hiroki Soeda, Atsushi Tachigami, Takeshi Iijima
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Publication number: 20200212176Abstract: A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.Type: ApplicationFiled: March 11, 2020Publication date: July 2, 2020Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Makoto KOSHIMIZU, Hideki NIWAYAMA, Kazuyuki UMEZU, Hiroki SOEDA, Atsushi TACHIGAMI, Takeshi IIJIMA
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Patent number: 10396029Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.Type: GrantFiled: June 11, 2018Date of Patent: August 27, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Koujirou Matsui, Takehiko Sakamoto, Kazuyuki Umezu, Tomoaki Uno
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Publication number: 20190189737Abstract: A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.Type: ApplicationFiled: February 14, 2019Publication date: June 20, 2019Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Makoto KOSHIMIZU, Hideki NIWAYAMA, Kazuyuki UMEZU, Hiroki SOEDA, Atsushi TACHIGAMI, Takeshi IIJIMA
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Publication number: 20180294220Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.Type: ApplicationFiled: June 11, 2018Publication date: October 11, 2018Inventors: Koujirou MATSUI, Takehiko SAKAMOTO, Kazuyuki UMEZU, Tomoaki UNO
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Patent number: 10074744Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.Type: GrantFiled: June 16, 2017Date of Patent: September 11, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hideo Numabe, Nobuyuki Shirai, Hirokazu Kato, Tomoaki Uno, Kazuyuki Umezu
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Patent number: 10068849Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.Type: GrantFiled: March 17, 2016Date of Patent: September 4, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Koujirou Matsui, Takehiko Sakamoto, Kazuyuki Umezu, Tomoaki Uno
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Patent number: 9866207Abstract: A driver integrated circuit includes a bootstrap circuit (BSC) configured to output a boot power supply voltage (VB) based on a first power supply voltage, the boot power supply voltage being higher than the first power supply voltage; a level shift circuit (LSC) configured to output an output pulse signal based on an input pulse signal and the boot power supply voltage; a high side driving circuit (HSU) configured to output a high side driving voltage based on the boot power supply voltage and the output pulse signal, wherein the bootstrap circuit includes a sense metal oxide semiconductor (MOS) transistor and a boot MOS transistor, wherein the sense MOS transistor includes a depression-type transistor.Type: GrantFiled: December 21, 2016Date of Patent: January 9, 2018Assignee: Renesas Electronics CorporationInventors: Ryo Kanda, Tetsu Toda, Junichi Nakamura, Kazuyuki Umezu, Tomonobu Kurihara, Takahiro Nagatsu, Yasushi Nakahara, Yoshinori Kaya
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Publication number: 20170288053Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.Type: ApplicationFiled: June 16, 2017Publication date: October 5, 2017Inventors: Hideo Numabe, Nobuyuki Shirai, Hirokazu Kato, Tomoaki Uno, Kazuyuki Umezu
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Patent number: 9711637Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.Type: GrantFiled: January 31, 2014Date of Patent: July 18, 2017Assignee: Renesas Electronics CorporationInventors: Hideo Numabe, Nobuyuki Shirai, Hirokazu Kato, Tomoaki Uno, Kazuyuki Umezu
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Publication number: 20170104474Abstract: A driver integrated circuit includes a bootstrap circuit (BSC) configured to output a boot power supply voltage (VB) based on a first power supply voltage, the boot power supply voltage being higher than the first power supply voltage; a level shift circuit (LSC) configured to output an output pulse signal based on an input pulse signal and the boot power supply voltage; a high side driving circuit (HSU) configured to output a high side driving voltage based on the boot power supply voltage and the output pulse signal, wherein the bootstrap circuit includes a sense metal oxide semiconductor (MOS) transistor and a boot MOS transistor, wherein the sense MOS transistor includes a depression-type transistor.Type: ApplicationFiled: December 21, 2016Publication date: April 13, 2017Inventors: Ryo KANDA, Tetsu TODA, Junichi NAKAMURA, Kazuyuki UMEZU, Tomonobu KURIHARA, Takahiro NAGATSU, Yasushi NAKAHARA, Yoshinori KAYA
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Patent number: 9559687Abstract: In order to reduce the cost and the like of a power control device including a semiconductor device such as a driver IC, as well as an electronic system, the driver IC includes a high side driver, a level shift circuit, first and second transistors, and a comparator circuit. The first transistor is formed in a termination area. The second transistor is formed in the termination region and is driven by a first power supply voltage. The comparator circuit is formed in a first region to drive the first transistor to be ON when the voltage of a sense node is lower than the first power supply voltage, while driving the first transistor to be OFF when the voltage of the sense node is higher than the first power supply voltage. The second transistor is a depression type transistor.Type: GrantFiled: August 21, 2015Date of Patent: January 31, 2017Assignee: Renesas Electronics CorporationInventors: Ryo Kanda, Tetsu Toda, Junichi Nakamura, Kazuyuki Umezu, Tomonobu Kurihara, Takahiro Nagatsu, Yasushi Nakahara, Yoshinori Kaya
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Publication number: 20160351702Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.Type: ApplicationFiled: January 31, 2014Publication date: December 1, 2016Inventors: Hideo Numabe, Nobuyuki Shirai, Hirokazu Kato, Tomoaki Uno, Kazuyuki Umezu
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Publication number: 20160204252Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.Type: ApplicationFiled: March 17, 2016Publication date: July 14, 2016Inventors: Koujirou MATSUI, Takehiko SAKAMOTO, Kazuyuki UMEZU, Tomoaki UNO
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Patent number: 9318434Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.Type: GrantFiled: August 27, 2014Date of Patent: April 19, 2016Assignee: RENSAS ELECTRONICS CORPORATIONInventors: Koujirou Matsui, Takehiko Sakamoto, Kazuyuki Umezu, Tomoaki Uno
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Publication number: 20160056818Abstract: In order to reduce the cost and the like of a power control device including a semiconductor device such as a driver IC, as well as an electronic system, the driver IC includes a high side driver, a level shift circuit, first and second transistors, and a comparator circuit. The first transistor is formed in a termination area. The second transistor is formed in the termination region and is driven by a first power supply voltage. The comparator circuit is formed in a first region to drive the first transistor to be ON when the voltage of a sense node is lower than the first power supply voltage, while driving the first transistor to be OFF when the voltage of the sense node is higher than the first power supply voltage. The second transistor is a depression type transistor.Type: ApplicationFiled: August 21, 2015Publication date: February 25, 2016Inventors: Ryo KANDA, Tetsu TODA, Junichi NAKAMURA, Kazuyuki UMEZU, Tomonobu KURIHARA, Takahiro NAGATSU, Yasushi NAKAHARA, Yoshinori KAYA
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Publication number: 20150137260Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.Type: ApplicationFiled: August 27, 2014Publication date: May 21, 2015Inventors: Koujirou MATSUI, Takehiko SAKAMOTO, Kazuyuki UMEZU, Tomoaki UNO
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Publication number: 20140173302Abstract: Miniaturization of a multiphase type power supply device can be achieved. A power supply control unit in which, for example, a microcontroller unit, a memory unit and an analog controller unit are formed over a single chip, a plurality of PWM-equipped drive units, and a plurality of inductors configure a multiphase power supply. The microcontroller unit outputs clock signals each having a frequency and a phase defined based on a program on the memory unit to the respective PWM-equipped drive units. The analog controller unit detects a difference between a voltage value of a load and a target voltage value acquired via a serial interface and outputs an error amp signal therefrom. Each of the PWM-equipped drive units drives each inductor by a peak current control system using the clock signal and the error amp signal.Type: ApplicationFiled: February 24, 2014Publication date: June 19, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Ryotaro KUDO, Tomoaki UNO, Koji TATENO, Hideo ISHII, Kazuyuki UMEZU, Koji SAIKUSA
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Patent number: 8680830Abstract: Miniaturization of a multiphase type power supply device can be achieved. A power supply control unit in which, for example, a microcontroller unit, a memory unit and an analog controller unit are formed over a single chip, a plurality of PWM-equipped drive units, and a plurality of inductors configure a multiphase power supply. The microcontroller unit outputs clock signals each having a frequency and a phase defined based on a program on the memory unit to the respective PWM-equipped drive units. The analog controller unit detects a difference between a voltage value of a load and a target voltage value acquired via a serial interface and outputs an error amp signal therefrom. Each of the PWM-equipped drive units drives each inductor by a peak current control system using the clock signal and the error amp signal.Type: GrantFiled: September 12, 2011Date of Patent: March 25, 2014Assignee: Renesas Electronics CorporationInventors: Ryotaro Kudo, Tomoaki Uno, Koji Tateno, Hideo Ishii, Kazuyuki Umezu, Koji Saikusa
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Publication number: 20130087828Abstract: A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.Type: ApplicationFiled: June 21, 2010Publication date: April 11, 2013Inventors: Makoto Koshimizu, Hideki Niwayama, Kazuyuki Umezu, Hiroki Soeda, Atsushi Tachigami, Takeshi Iijima