Patents by Inventor Kazuyuki Yahiro

Kazuyuki Yahiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8395138
    Abstract: A nonvolatile semiconductor memory using carbon related films as variable resistance films includes bottom electrodes formed above a substrate, buffer layers formed on the bottom electrodes and each formed of a film containing nitrogen and containing carbon as a main component, variable resistance films formed on the buffer layers and each formed of a film containing carbon as a main component and the electrical resistivity thereof being changed according to application of voltage or supply of current, and top electrodes formed on the variable resistance films.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: March 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Yamamoto, Kazuyuki Yahiro, Tsukasa Nakai
  • Patent number: 8334525
    Abstract: According to one embodiment, a variable resistance layer includes a mixture of a first compound and a second compound. The first compound includes carbon (C) as well as at least one element selected from a group of elements G1. The group of elements G1 consists of hydrogen (H), boron (B), nitrogen (N), silicon (Si), and titanium (Ti). The second compound includes at least one compound selected from a group of compounds G2. The group of compounds G2 consists of silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (Si3N4), carbon nitride (C3N4), boron nitride (BN), aluminum nitride (AlN), aluminum oxide (Al2O3), and silicon carbide (SiC). Concentration of the first compound in the variable resistance layer is not less than 30 volume percent, and not more than 70 volume percent.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: December 18, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsukasa Nakai, Hiroyuki Fukumizu, Yasuhiro Nojiri, Motoya Kishida, Kazuyuki Yahiro, Yasuhiro Satoh
  • Patent number: 8329385
    Abstract: A method of manufacturing a semiconductor device according to one embodiment, includes: forming a first mask material film on a workpiece film formed on a semiconductor substrate; forming a resist pattern on the first mask material film; forming a second mask material film having a desired film thickness on the first mask material film so as to cover the resist pattern; carrying out etchback of the second mask material film so as to expose the resist pattern and the first mask material film; processing the resist pattern and the first mask material film simultaneously which are exposed, while leaving the second mask material film of which etchback is carried out; and processing the workpiece film which exposes under the first mask material film.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: December 11, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eishi Shiobara, Keisuke Kikutani, Kazuyuki Yahiro, Kentaro Matsunaga, Tomoya Oori
  • Patent number: 7960764
    Abstract: Disclosed is a semiconductor device manufacturing method in which a silicon nitride film is formed to cover an n-channel transistor formed on a semiconductor substrate and to apply a tensile stress in a channel length direction to a channel of the n-channel transistor, the method includes: forming a first-layer silicon nitride film above the n-channel transistor; irradiating the first-layer silicon nitride film with ultraviolet radiation; and after the ultraviolet irradiation, forming at least one silicon nitride film thinner than the first-layer silicon nitride film above the first-layer silicon nitride film. Silicon nitride films formed to apply the tensile stress is formed by respective steps.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: June 14, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiaki Idaka, Kazuyuki Yahiro
  • Publication number: 20100327253
    Abstract: According to one embodiment, a variable resistance layer includes a mixture of a first compound and a second compound. The first compound includes carbon (C) as well as at least one element selected from a group of elements G1. The group of elements G1 consists of hydrogen (H), boron (B), nitrogen (N), silicon (Si), and titanium (Ti). The second compound includes at least one compound selected from a group of compounds G2. The group of compounds G2 consists of silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (Si3N4), carbon nitride (C3N4), boron nitride (BN), aluminum nitride (AlN), aluminum oxide (Al2O3), and silicon carbide (SiC). Concentration of the first compound in the variable resistance layer is not less than 30 volume percent, and not more than 70 volume percent.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 30, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsukasa NAKAI, Hiroyuki FUKUMIZU, Yasuhiro NOJIRI, Motoya KISHIDA, Kazuyuki YAHIRO, Yasuhiro SATOH
  • Publication number: 20100320512
    Abstract: Disclosed is a semiconductor device manufacturing method in which a silicon nitride film is formed to cover an n-channel transistor formed on a semiconductor substrate and to apply a tensile stress in a channel length direction to a channel of the n-channel transistor, the method includes: forming a first-layer silicon nitride film above the n-channel transistor; irradiating the first-layer silicon nitride film with ultraviolet radiation; and after the ultraviolet irradiation, forming at least one silicon nitride film thinner than the first-layer silicon nitride film above the first-layer silicon nitride film. Silicon nitride films formed to apply the tensile stress is formed by respective steps.
    Type: Application
    Filed: August 25, 2010
    Publication date: December 23, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshiaki Idaka, Kazuyuki Yahiro
  • Patent number: 7803706
    Abstract: Disclosed is a semiconductor device manufacturing method in which a silicon nitride film is formed to cover an n-channel transistor formed on a semiconductor substrate and to apply a tensile stress in a channel length direction to a channel of the n-channel transistor, the method includes: forming a first-layer silicon nitride film above the n-channel transistor; irradiating the first-layer silicon nitride film with ultraviolet radiation; and after the ultraviolet irradiation, forming at least one silicon nitride film thinner than the first-layer silicon nitride film above the first-layer silicon nitride film. Silicon nitride films formed to apply the tensile stress is formed by respective steps.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: September 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiaki Idaka, Kazuyuki Yahiro
  • Publication number: 20100181546
    Abstract: A nonvolatile semiconductor memory using carbon related films as variable resistance films includes bottom electrodes formed above a substrate, buffer layers formed on the bottom electrodes and each formed of a film containing nitrogen and containing carbon as a main component, variable resistance films formed on the buffer layers and each formed of a film containing carbon as a main component and the electrical resistivity thereof being changed according to application of voltage or supply of current, and top electrodes formed on the variable resistance films.
    Type: Application
    Filed: August 21, 2009
    Publication date: July 22, 2010
    Inventors: Kazuhiko Yamamoto, Kazuyuki Yahiro, Tsukasa Nakai
  • Publication number: 20090305166
    Abstract: A method of manufacturing a semiconductor device according to one embodiment, includes: forming a first mask material film on a workpiece film formed on a semiconductor substrate; forming a resist pattern on the first mask material film; forming a second mask material film having a desired film thickness on the first mask material film so as to cover the resist pattern; carrying out etchback of the second mask material film so as to expose the resist pattern and the first mask material film; processing the resist pattern and the first mask material film simultaneously which are exposed, while leaving the second mask material film of which etchback is carried out; and processing the workpiece film which exposes under the first mask material film.
    Type: Application
    Filed: June 10, 2009
    Publication date: December 10, 2009
    Inventors: Eishi SHIOBARA, Keisuke Kikutani, Kazuyuki Yahiro, Kentaro Matsunaga, Tomoya Oori
  • Publication number: 20090283874
    Abstract: Disclosed is a semiconductor device manufacturing method in which a silicon nitride film is formed to cover an n-channel transistor formed on a semiconductor substrate and to apply a tensile stress in a channel length direction to a channel of the n-channel transistor, the method includes: forming a first-layer silicon nitride film above the n-channel transistor; irradiating the first-layer silicon nitride film with ultraviolet radiation; and after the ultraviolet irradiation, forming at least one silicon nitride film thinner than the first-layer silicon nitride film above the first-layer silicon nitride film. Silicon nitride films formed to apply the tensile stress is formed by respective steps.
    Type: Application
    Filed: March 20, 2009
    Publication date: November 19, 2009
    Inventors: Toshiaki IDAKA, Kazuyuki Yahiro
  • Publication number: 20050145482
    Abstract: An apparatus and a method for processing substrate are generally used for apparatuses for wet-type process of substrate, such as an electrolytic processing apparatus for use in forming interconnects by embedding a metal such as copper (Cu) or the like in fine interconnect patterns (recesses) that are formed in a substrate such as a semiconductor wafer and for use in forming bumps for electrical connections.
    Type: Application
    Filed: October 27, 2004
    Publication date: July 7, 2005
    Inventors: Hidenao Suzuki, Koji Mishima, Hiroyuki Kanda, Kazufumi Nomura, Kunihito Ide, Kazuyuki Yahiro, Hiroshi Toyoda, Tetsuo Matsuda
  • Publication number: 20050145500
    Abstract: According to an embodiment of the present invention, a plating apparatus, including: a plating solution tank configured to store a plating solution; a holder configured to hold a substrate on which a seed layer is formed in said plating solution tank; a first anode disposed in said plating solution tank, composed of a more anodic material in its oxidation-reduction potential than the oxidation-reduction potential of a metal composing the seed layer, and electrically connectable to the seed layer of the substrate held by said holder; and a second anode disposed in said plating solution tank, capable of applying a voltage between the seed layer of the substrate held by holder, is provided.
    Type: Application
    Filed: November 30, 2004
    Publication date: July 7, 2005
    Inventors: Hiroshi Toyoda, Yoshitaka Matsui, Kazuyuki Yahiro, Junsei Yamabe, Shiro Mishima, Takahito Nagamatsu
  • Patent number: 6153542
    Abstract: In a method of manufacturing a semiconductor device, a first plasma insulating film having a thickness of 0.1 .mu.m or more is formed on the semiconductor substrate with lower-surface wirings thereon. The semiconductor substrate is moved into a pressure-reduced CVD device, and then an SiH.sub.4 gas and H.sub.2 O.sub.2 are supplied into the pressure-reduced CVD device to react them to each other in a vacuum of 650 Pa or less within the temperature range of -10.degree. C. to +10.degree. C. to form a reflow SiO.sub.2 film having a thickness of 0.4 .mu.m to 1.4 .mu.m on the semiconductor substrate. The semiconductor substrate is put in a vacuum of 6.5 pascal for 30 seconds or more. Thereafter, the semiconductor substrate is put at a high temperature of 300.degree. C. to 450.degree. C. for 120 to 600 seconds. A second plasma insulating film having a thickness of 0.3 .mu.m or more and serving as a cap film is formed on the semiconductor substrate.
    Type: Grant
    Filed: May 23, 1997
    Date of Patent: November 28, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuyuki Yahiro
  • Patent number: 5683940
    Abstract: In a method of manufacturing a semiconductor device, a first plasma insulating film having a thickness of 0.1 .mu.m or more is formed on the semiconductor substrate with lower-surface wirings thereon. The semiconductor substrate is moved into a pressure-reduced CVD device, and then an SiH.sub.4 gas and H.sub.2 O.sub.2 are supplied into the pressure-reduced CVD device to react them to each other in a vacuum of 650 Pa or less within the temperature range of -10.degree. C. to +10.degree. C. to form a reflow SiO.sub.2 film having a thickness of 0.4 .mu.m to 1.4 .mu.m on the semiconductor substrate. The semiconductor substrate is put in a vacuum of 6.5 pascal for 30 seconds or more. Thereafter, the semiconductor substrate is put at a high temperature of 300.degree. C. to 450.degree. C. for 120 to 600 seconds. A second plasma insulating film having a thickness of 0.3 .mu.m or more and serving as a cap film is formed on the semiconductor substrate.
    Type: Grant
    Filed: December 20, 1995
    Date of Patent: November 4, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuyuki Yahiro
  • Patent number: 5661078
    Abstract: In a semiconductor device according to the present invention, a diffusion layer is formed on a silicon substrate, and a Silicon oxide film is deposited thereon. A hole communicating with the diffusion layer is formed in the silicon oxide film. A silver bromide emulsion is applied to the silicon oxide film having the hole by the spin coat technique. The silver bromide emulsion is irradiated with light through a mask to leave only that portion of the emulsion which is exposed by the light. By doing so, a metal wiring is formed integrally with a via hole, and thus decreased in resistance and suitable for forming the via hole. Consequently, a semiconductor device having such a wiring can be obtained easily, inexpensively.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: August 26, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyuki Yahiro, Shuji Itonaga