Abstract: An array substrate having a display area, a peripheral area, and a bonding area inside the peripheral area is provided. The array substrate includes a bonding pad in the bonding area, the bonding pad configured to be connected to a peripheral circuit through a bonding connector, a test signal line including a first portion and a second portion. The first portion is in the peripheral area and substantially surrounds the display area. The first portion is electrically connected to the bonding pad. The first portion is completely inside the array substrate and has no exposed terminal. The second portion is in the bonding area. A first terminal of the second portion is electrically connected to the bonding pad. A second terminal of the second portion has an end along an edge of the array substrate in the bonding area.

Abstract: The disclosure relates to a display substrate. The display substrate may include a semiconductor pattern and a first conductive pattern stacked on a base substrate, and a second conductive pattern electrically connected to the first conductive pattern. A first orthographic projection of the first conductive pattern on the base substrate may fall within a second orthographic projection of the semiconductor pattern on the base substrate, and a distance between the second orthographic projection and a fourth orthographic projection of a display electrode of the display substrate on the base substrate ma be greater than a distance between a third orthographic projection of the second conductive pattern on the base substrate and the fourth orthographic projection.

Abstract: The present disclosure relates to the field of display technology, and provides a display module and a display device. The display module includes a first display sub-panel, where the first display sub-panel includes: a first display sub-panel including a plurality of first pixel units; and a second display sub-panel arranged at a light-entering side of the first display sub-panel and including a plurality of second pixel units. Each second pixel unit corresponds to at least one first pixel unit, an orthogonal projection of each second pixel unit onto the first display sub-panel coincides with the corresponding first pixel unit, and the second display sub-panel is a vertical-electric-field-type liquid crystal display panel.

Abstract: An aging device for a display panel includes: a bearing device, including a bearing surface that is configured to bear the display panel; a fixture, including a plurality of pins which are configured to provide a screen turning-on signal for the display panel; a first electrode and a second electrode, wherein the first electrode and the second electrode are in an opposite arrangement and configured to apply an electric field to the display panel. The aging device achieves aging by providing an electric field for the display panel, avoids the burning of the thin film transistor devices of the display panel caused by the excessive bias and allows the thin film transistors at different positions to be uniformly aged, and is also easy to operate and implement.

Abstract: Provided are a shift register and a driving method thereof, a gate driving circuit, and a display apparatus. The shift register is disposed on a display panel. An operating process of the display panel includes a start-up phase and a display phase. The shift register includes a shift register unit, a start-up discharge circuit, a first control end, a second control end, a signal output end and a first power supply end; the shift register unit is configured to output a gate driving signal to the signal output end in the display phase; the start-up discharge circuit is configured to provide a signal of the first power supply end to the signal output end under control of the first control end and the second control end in the start-up phase.

Abstract: A gray-scale drive table generating device is described that includes a sampling circuit configured to collect a first voltage between a drive electrode of a sub-pixel of a positive-frame and a common electrode and a second voltage between a drive electrode of a sub-pixel of a negative-frame and the common electrode in a display panel in each gray-scale; a processing circuit configured to generate a trigger signal when a voltage difference between the first voltage and the second voltage is greater than a voltage threshold; an adjustment circuit configured to adjust drive gray-scales of the sub-pixel of the positive-frame and/or the sub-pixel of the negative-frame in response to the trigger signal to make the voltage difference less than the voltage threshold; and a recording circuit configured to generate an adjusted gray-scale drive table according to the drive gray-scales of the sub-pixel of the positive-frame and the sub-pixel of the negative-frame in each gray-scale.

Abstract: A display device, a gate drive circuit, a shift register and a control method are disclosed. A first shift register unit of the shift register is configured to write a first control signal to a first node under control of a first input signal, write a first clock signal to a first signal output terminal; a second shift register unit of the shift register is configured to write a second control signal to the first node under control of a second input signal, write a second clock signal to a second signal output terminal; during the first frame, the first clock signal and the first input signal are pulse signals, the second clock signal and the second input signal are DC signals; during the second frame, the first clock signal and the first input signal are DC signals, the second clock signal and the second input signal are pulse signals.

Abstract: The present disclosure relates to a display panel. The display panel may include a first substrate, a second substrate opposite the first substrate, and a frame supporting structure between the first substrate and the second substrate in a frame area of the display panel. The frame area of the display panel may surround a display area of the display panel. The frame supporting structure may include a first frame supporting portion on at least one part of a circumference of the display area, the first frame supporting portion comprises an elastic material, and an elastic recovery rate of the elastic material is above about 80%.

Abstract: An array substrate, a method of manufacturing the same, and a display panel are provided. The method includes: providing a base substrate including a display area and a wiring area at a periphery of the display area; in the process of forming a connection electrode in the wiring area, remaining a first photoresist layer for performing the patterning process and covering the connection electrode; depositing a film of reflective pixel electrode layer on the base substrate and performing a patterning process on the film of reflective pixel electrode layer to form a reflective pixel electrode layer in the display area and to remove the film of reflective pixel electrode layer in the wiring area to expose the first photoresist layer; removing a second photoresist layer for patterning the thin film of reflective pixel electrode layer on the reflective pixel electrode layer with the first photoresist layer in the wiring area.

Abstract: A display apparatus includes a first polarizer, a first liquid crystal panel, a second polarizer, a second liquid crystal panel and a third polarizer which are sequentially stacked, wherein the second polarizer includes two protective layers, and a polarizing layer positioned between the two protective layers.

Abstract: A common voltage calibration circuit and a driving method thereof, a circuit board and a display device are provided. The common voltage calibration circuit includes a difference circuit, a compensation circuit and a summing circuit; the difference circuit is configured to perform a difference processing on a common voltage provided by the common voltage input terminal and a feedback common voltage provided by the common voltage feedback terminal to output a difference value signal; the compensation circuit is configured to receive the difference value signal and compensate the common voltage based on the difference value signal; and the summing circuit is configured to superimpose at least two compensation signals output by the compensation circuit and output through the common voltage output terminal.

Abstract: The present application provides an apparatus for a photo-alignment process. The apparatus for a photo-alignment process includes a reflector, an up-conversion layer, and a polarizer optically coupled together. The reflector is configured to reflect an infrared light and provide a reflected infrared light to the up-conversion layer. The up-conversion layer is configured to convert the reflected infrared light to an ultraviolet light, and provide the ultraviolet light to the polarizer. The polarizer is configured to convert the ultraviolet light to a polarized ultraviolet light for the photo-alignment process.

Abstract: A display panel having a display area and a peripheral area is provided. The display panel includes a first display substrate; a second display substrate facing the first display substrate; a sealant layer in the peripheral area and between the first display substrate and the second display substrate, configured to seal the first display substrate and the second display substrate together to form a cell; and an elastic support layer in the peripheral area and between the first display substrate and the second display substrate. The elastic support layer encircled by the sealant layer and spaced apart from the sealant layer. The elastic support layer substantially surrounds the display area. The elastic support layer is configured to be in direct contact with the first display substrate and in direct contact with the second display substrate.

Abstract: A display driving device, a display driving method, a display module and a display device are provided. The display driving device includes: a PWM signal generating circuit configured to generate a PWM signal; a PWM signal acquisition circuit, configured to identify whether the PWM signal output by the PWM signal generating circuit is at a high level or a low level; a gamma voltage debugging circuit, configured to debug a gamma voltage to obtain a first group of gamma voltage reference data corresponding to the PWM signal at the high level and a second group of gamma voltage reference data corresponding to the PWM signal at the low level in each gray-scale image; and a gamma voltage switching circuit.

Abstract: The present disclosure relates to a display panel and a display device. The display panel comprises: a display liquid crystal panel comprising a plurality of sub-pixels defined by a first grid structure and arranged in an array; a dimming liquid crystal panel located on a light incident side of the display liquid crystal panel and stacked with the display liquid crystal panel, the dimming liquid crystal panel comprising a plurality of dimming pixels defined by a second grid structure and arranged in an array; wherein the second grid structure comprises a plurality of shading lines which extend in a waveform along a row direction and have the same period, and a waveform phase difference ?? of any two adjacent shading lines meets: 0<|??|<?.

Abstract: The present disclosure provides a circuit control method and a control device, a display module and a display device. The circuit control device is used for acquiring an indication signal for indicating whether a user performs touch operation on the touch panel or not; the current is provided for the driving circuit according to the indication signal, a first current is provided for the driving circuit under the condition that a user does not carry out touch operation on the touch panel, a second current is provided for the driving circuit under the condition that the user carries out touch operation on the touch panel, and the second current is larger than the first current.

Abstract: An array substrate is disclosed, the array sul cluding: a pixel display transistor having a first source, a first drain, and a first channel region, the first channel region having a first channel length extending between the first source and the first drain; an antistatic transistor having a second source, a second drain, and a second channel region; and a conductive block in the second channel region between the second source and the second drain; wherein the first channel region and second channel region are patterned regions of a same semiconductor material layer; and the conductive block divides the second channel region into a first sub-channel and a second sub-channel.

Abstract: The present disclosure generally relates to display technologies. An array substrate includes a plurality of repeating units arranged in a first direction, each repeating unit including a plurality of connection areas and a plurality of shared testing areas arranged in an alternating manner in a row along the first direction. Each of the plurality of shared testing areas is between two adjacent connection areas and coupled to each of the two adjacent connection areas, and each of the plurality of shared testing areas includes a plurality of testing pads, a first portion of the plurality of testing pads being coupled to one of the two adjacent connection areas, a second portion of the plurality of testing pads being coupled to the other one of the two adjacent connection areas.

Abstract: A chip-on-film and a display device. The chip-on-film includes a substrate, at least one chip on the substrate, input terminals on the substrate, and output terminals on the substrate. The input terminals are configured to receive printed-circuit-board signals. The output terminals include data signal output sub-terminals configured to output display panel data signals. The output terminals lack an output sub-terminal configured to output a display panel scanning signal.

Abstract: A driver control circuit and a display device are disclosed, where the driver control circuit includes: a first transistor with a first terminal connected with a supply voltage of a main loop, and a second terminal connected with a first ground terminal; and a first control component connected with a control terminal of the first transistor, and configured to control the first transistor to be in a state of incomplete conduction in amplification region, when the supply voltage of the main loop is powered on.