Abstract: A display device and a manufacturing method thereof, an electronic device, and a light control panel are provided. The display device includes a light control panel and a display liquid crystal panel. The display liquid crystal panel is on a light-emitting side of the light control panel; the light control panel includes a light control region, and the light control region is configured to provide adjusted backlight to the display liquid crystal panel; the display liquid crystal panel includes a display region, and the display region is configured to receive the adjusted backlight to perform display; and a distance between two opposite edges of the light control region in at least one direction is greater than a distance between two opposite edges of the display region in the at least one direction.

Abstract: Systems and methods are provided for performing random walk graph computing. One method may comprise generating a subset of walkers on a graph, maintaining the generated subset of walkers in a walker pool in a memory, loading a coarse-grained block of the graph from a non-volatile storage into a block buffer of the memory, generating pre-sampled edges for vertices in the coarse-grained block, storing the pre-sampled edges into a pre-sampled edge buffer allocated for the coarse-grained block and moving one or more walkers of the generated subset of walkers using the pre-sampled edges stored in the pre-sampled edge buffer. The generated subset of walkers may have an initial number determined based on a memory space allocated to the walker pool.

Abstract: In certain aspects, a memory device includes a memory string including a drain select gate (DSG) transistor, a plurality of memory cells, and a source select gate (SSG) transistor, and a peripheral circuit coupled to the memory string. The peripheral circuit is configured to in response to an interrupt during a program operation on a select memory cell of the plurality of memory cells, turn on at least one of the DSG transistor or the SSG transistor. The peripheral circuit is also configured to suspend the program operation after turning on the at least one of the DSG transistor or the SSG transistor.

Abstract: In certain aspects, a memory device includes memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is configured to initiate a program operation on a selected memory cell of the memory cells, obtain a number of occurrences of one or more suspensions during the program operation, and determine a program pulse limit for the program operation based on the number of occurrences of the suspensions.

Abstract: A cell structure of an insulated gate bipolar transistor (IGBT) with a control gate and a carrier storage layer, is provided including: an N-type drift layer with a first surface, an active region on a second surface opposing the first and an N-type storage layer, a P-type body layer and an N-type doped layer sequentially stacked in the active region from the first to the second surface, gate trench bodies, each of which extends from the second to the first surface in a first direction perpendicular to the first surface and contacts the N-type drift layer, and each of the at least three gate trench bodies is a gate trench or a control gate trench. A sidewall of the gate trench is in contact with the active region, and a sidewall of the control gate trench is in contact with the P-type layer but not with the N-type layer.

Abstract: The disclosure provides power semiconductor modules and their assembling methods. The module includes a heat-dissipation contact area, a housing and a press-on element. One of the housing and the press-on element includes a rail portion, while the other includes a rail cooperating portion. The housing and the press-on element respectively includes a first limiting portion and a first limiting cooperating portion. The rail cooperating portion can be inserted into the rail portion and slides on the rail portion in the direction toward or away from the plane where the heat-dissipation contact area is located, so that the press-on element could move from the separation position to the mounted position connected with the housing. The rail portion can cooperate with the rail cooperating portion to prevent the press-on element from moving relative to the housing in the direction parallel to the plane where the heat-dissipation contact area is located.

Abstract: A semiconductor device and a manufacturing method thereof is provided. The device includes a semiconductor layer having a first and second surface opposing each other; a trench gate in the semiconductor layer, extends in a first direction parallel to the first and second surface, and from the first surface to an interior of the layer, and has a gate open end distant from the second surface; a source region of a first conductivity type and a channel region of a second conductivity type, orthographic projections of the source region and the channel region on the second surface at least partially overlap with each other in a depth direction of the trench gate, the source region having a source open end distant from the second surface, and the farther the source open end is from the second surface, the smaller a width of the source open end in the second direction.

Abstract: This disclosure describes a machine learning system that includes a contrastive learning based two-tower model for retrieval of relevant chemical reaction procedures given a query chemical reaction. The two-tower model uses attention-based transformers and neural networks to convert tokenized representations of chemical reactions and chemical reaction procedures to embeddings in a shared embedding space. Each tower can include a transformer network, a pooling layer, a normalization layer, and a neural network. The model is trained with labeled data pairs that include a chemical reaction and the text of a chemical reaction procedure for that chemical reaction. New queries can locate chemical reaction procedures for performing a given chemical reaction as well as procedures for similar chemical reactions. The architecture and training of the model make it possible to perform semantic matching based on chemical structures. The model is highly accurate providing an average recall at K=5 of 95.9%.

Abstract: A memory device is disclosed. The memory device may include a memory string and a peripheral circuit. The memory string may include a drain select gate (DSG) transistor, a plurality of memory cells, and a source select gate (SSG) transistor. The peripheral circuit may be coupled to the memory string and configured to, during a program operation on a select memory cell of the plurality of memory cells: after detecting an interrupt signal, perform a clean process that includes turning on at least one of the DSG transistor or the SSG transistor.

Abstract: A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes: a semiconductor body having a first surface and a second surface, the semiconductor body includes: a depletion region, a drift region having a first conductivity type, an island region having the first conductivity type, a buffer region having the first conductivity type, the drift region is more proximal to the first surface of the semiconductor body than the buffer region, the depletion region is located within the drift region, and the island region is located within the drift region, an ion concentration of the first conductivity type of the island region is higher than an ion concentration of the first conductivity type of the drift region.

Abstract: A package structure for a power semiconductor device is provided, including: a substrate; two or more semiconductor dies on the substrate, each of the semiconductor dies includes a first power switching pad, a second power switching pad and a gate; a gate control conductive trace, a first power switching contact and a second power switching contact are further arranged on the substrate, the gate control conductive trace is connected to each of the semiconductor dies via a bonding component, and the bonding component connecting a first semiconductor die to the gate control conductive trace is sandwiched between circuit lines formed by connecting the second power switching pads of the first semiconductor die and the neighboring second semiconductor die, to second power switching contact of the substrate.

Abstract: This disclosure provides a design method for a radiator of a vehicle power module. The design method includes: selecting a plurality of specific values from the possible value ranges of the first distance D1, the second distance D2 and the radius R, respectively, to form different combinations of the plurality of specific values, performing simulation calculations on the different combinations, and obtaining a temperature rise ?Tj and a pressure drop ?Pf corresponding to each combination to form a plurality of samples; through a response surface method, fitting explicit functions of the temperature rise ?Tj and the pressure drop ?Pf with the first distance D1, the second distance D2 and the radius R as dependent variables; and through a multi-objective optimization, determining the first distance D1, the second distance D2 and the radius R with an optimization objective that the temperature rise ?Tj and the pressure drop ?Pf are simultaneously minimized.

Abstract: Disclosed herein is a model flow that generates eligibility criteria for a clinical trial based on eligibility criteria associated with a protocol title of the trial. Unlike standard black-box generation models, the techniques disclosed herein leverage existing knowledge to enhance the title. The enhanced title also acts as an intermediate between the title and the generated criteria clauses, enabling explicit control of the generated content as well as an explanation of why the generated content is relevant. The resulting workflow is knowledge-grounded, controllable, transparent, and interpretable.

Abstract: A memory system includes a memory cell array and a controller coupled to the memory cell array. The controller is configured to control applying a first program voltage to a word line to program memory cells in the memory cell array, the memory cells being coupled to the word line, and in response to receiving a suspend command, control applying a positive bias discharge voltage to the word line when the first program voltage ramps down.

Abstract: A method for programming a memory device, a memory device, and a memory system are disclosed. The memory device includes planes. The method includes: programming the planes by using a programming voltage incremented with a first step size; verifying the planes, and in response to determining that one or more planes are with a verification exception, disabling the one or more planes with the verification exception; and in response to the one or more planes with the verification exception being disabled, programming remaining one or more planes that are not disabled by using an other programming voltage incremented with a second step size less than the first step size.

Abstract: In certain aspects, a memory device includes memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is configured to initiate a program operation on a selected memory cell of the memory cells, obtain a number of occurrences of one or more suspensions during the program operation, and determine a program pulse limit for the program operation based on the number of occurrences of the suspensions.

Abstract: Embodiments of the present disclosure provide a method and apparatus for configuring a security carrier, including: adding a carrier batch field to a security carrier list, encoding, for each security carrier in the security carrier list, a plurality of pieces of batch feature information of the security carrier according to a preset encoding rule, so as to generate carrier batch information of each security carrier, and to add same to the security carrier list; and then, according to identifier information and the carrier batch information of each security carrier, configuring a supplementary security domain, a card application, an application installation package and an application provider that need to be preset for each security carrier.

Abstract: Provided is an AlGaN unipolar carrier solar-blind ultraviolet detector that is based on the AlGaN polarization effect and that uses the double heterojunction of the p-AlzGa1-zN/i-AlyGa1-yN/n-AlxGa1-xN (0.45=<x,z<y) as the main structure of the detector. It makes full use of the polarization built-in electric field pointing from n-type AlGaN to p-type AlGaN to enhance the electric field strength of the i-type absorption region and enhance the efficiency of carrier absorption and separation. At the same time, the valence band step of the p-AlzGa1-zN/i-AlyGa1-yN heterojunction is used to effectively restrict holes from entering the absorption region to recombine with electrons, thereby increasing the carrier lifetime. Furthermore, during device manufacturing the structure is such designed that makes it difficult for photo-generated holes to participate in the photoconductivity so as to realize unipolar conduction of electrons, thereby obtaining a high response speed and high gain current.

Abstract: The present disclosure relates to a method comprising: receiving a resource model associated with a resource site and receiving one or more objective parameters, such that a first objective parameter comprised in the one or more objective parameters is a function of one or more parameter values of the resource model. The method comprises executing simulations to generate a first uncertainty value based on at least one of a first parameter value and a first uncertainty value of a first parameter of the resource model. The simulations may be executed to generate a first forecast uncertainty value for each scenario comprised in a plurality of scenarios. The method also identifies one service that minimizes an uncertainty value of the objective parameter based on the forecast uncertainty value. The method further includes generating a first visualization comprising the one identified service for viewing by a user via a user interface.

Abstract: The present disclosure relates to a system that is operable to receive an execution plan and execute a control operation on one or more equipment based operations within the execution plan. The one or more operations may include a data capturing operation associated with a resource site. In one embodiment, the system may be operable to execute at least a first operation in response to a success variable of the data capturing operation indicating a successful execution of the data capturing operation. The first operation may include a quality control operation that is executed by comparing at least one characteristic of the captured data to an expected characteristic to generate quality state data. The quality state data may have one of an acceptable status and an undesirable status. In response to the quality state data indicating an acceptable status for the quality control operation, executing at least a second operation.