Patents by Inventor Ke Liang
Ke Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990481Abstract: The present disclosure provides an array substrate and a manufacturing method thereof, a display panel and a backlight module. The manufacturing method of the array substrate includes: providing a base substrate; forming a metal wiring layer on a side of the base substrate, the metal wiring layer including a first copper metal layer; forming a planarization layer on a side of the metal wiring layer away from the base substrate; forming a drive lead layer on a side of the planarization layer away from the base substrate, the drive lead layer being electrically connected to the metal wiring layer, the drive lead layer including a second copper metal layer with a thickness larger than that of the first copper metal layer; forming a functional device layer on a side of the drive lead layer away from the base substrate.Type: GrantFiled: September 18, 2020Date of Patent: May 21, 2024Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Zhanfeng Cao, Ke Wang, Zhiwei Liang, Jianguo Wang, Guocai Zhang, Xinhong Lu, Qi Qi
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Publication number: 20240152485Abstract: This application provides a data switching apparatus and a data switching method. The data switching apparatus includes a plurality of dies, the plurality of dies include a plurality of die sets. Each die in the plurality of die sets is coupled to a die in a same die set and a die in a different die set through corresponding interfaces.Type: ApplicationFiled: January 12, 2024Publication date: May 9, 2024Inventors: Yu Liang, Renjie Qu, Ke Zhang, Yan Zhao, Wan Lam
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Patent number: 11972815Abstract: The memory device includes a controller that is configured to program a plurality of memory cells of a selected word line in a plurality of programming loops and count the number of programming loops to complete programming. The controller is also configured to compare the number of programming loops to complete programming of the memory cells of the selected word line to at least one of a predetermined upper limit and a predetermined lower limit to determine if a plane containing the selected word line is at an elevated risk for read failure. In response to the controller making a determination that the plane containing the selected word line is at an elevated risk for read failure, the controller is configured to conduct a post write read operation at least one word line of the plurality of word lines.Type: GrantFiled: May 10, 2022Date of Patent: April 30, 2024Assignee: SanDisk Technologies, LLCInventors: Ke Zhang, Minna Li, Li Liang
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Publication number: 20240088170Abstract: An array substrate including a display area having a plurality of subpixels is provided. The plurality of subpixels includes a plurality of first subpixels in a display-bonding sub-area and a plurality of second subpixels in a regular display sub-area. The array substrate includes a plurality of thin film transistors on a first side of the base substrate and respectively in the plurality of subpixels. A respective one of the plurality of first subpixels includes a bonding pad on a second side of a base substrate; a lead line electrically connecting a respective one of a plurality of thin film transistors to the bonding pad; and a via extending through the base substrate. The lead line is unexposed in the array substrate. The lead line extends from the first side to the second side of the base substrate through the via, to connect to the bonding pad.Type: ApplicationFiled: November 23, 2023Publication date: March 14, 2024Applicant: BOE Technology Group Co., Ltd.Inventors: Ke Wang, Muxin Di, Zhiwei Liang, Guoqiang Wang, Renquan Gu, Xiaoxin Song, Xiaoyan Zhu, Yingwei Liu, Zhanfeng Cao
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Publication number: 20240087654Abstract: The present disclosure provides a method for controlling a 3D NAND memory using a read operation. The method can include increasing a voltage to a plurality of top select gates, with respect to a first reference voltage level, during a pre-pulse period of the read operation prior to a read period of the read operation. The method can also include increasing a voltage to a plurality of word lines, with respect to a second reference voltage level, during the pre-pulse period. The method can also include decreasing a voltage to a bit line, with respect to the first voltage, during the pre-pulse period. The method can also include applying no voltage change to a bottom select gate during the pre-pulse period.Type: ApplicationFiled: September 13, 2022Publication date: March 14, 2024Applicant: YANGTZE MEMORY TECHNOLOGIES., LTD.Inventors: Zhipeng DONG, Ke Liang, Liang Qiao
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Publication number: 20240085717Abstract: Disclosed are a super-resolution imaging system (1, 41, 51), a super-resolution imaging method, a biological sample identification system (4, 61) and method, a nucleic acid sequencing imaging system (5) and method, and a nucleic acid identification system (6) and method. The super-resolution imaging system (1, 41, 51) includes an illumination system (A) and an imaging system (B). The illumination system (A) outputs excitation light to irradiate a biological sample to generate excited light, and the imaging system (B) collects and records the excited light to generate an excited light image. The illumination system (A) includes an excitation light source (10, 10a) and a structured light generation and modulation device (11, 11a). The excitation light source (10, 10a) outputs the excitation light, and the structured light generation and modulation device (11, 11a) modulates the excitation light into structured light to irradiate the biological sample to generate the excited light.Type: ApplicationFiled: March 9, 2020Publication date: March 14, 2024Inventors: JIELEI NI, MING NI, FAN ZHOU, ZEYU SU, KE JI, DONG WEI, MENGZHE SHEN, YUANQING LIANG, MEI LI, XUN XU
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Patent number: 11929358Abstract: Provided is a display backplate including an array substrate and a plurality of pairs of connection structures on the array substrate, wherein the array substrate includes a plurality of thin-film transistors and a common electrode signal line, wherein at least one of the plurality of thin-film transistors is connected to one of a pair of connection structures and the common electrode signal line is connected to the other of the pair of connection structures; and an area of a first section of the connection structure is negatively correlated with a distance between the first section and a surface of the array substrate, and the first section is parallel to the surface of the array substrate.Type: GrantFiled: April 21, 2023Date of Patent: March 12, 2024Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Zhiwei Liang, Wenqian Luo, Yingwei Liu, Ke Wang, Qi Yao, Huijuan Wang, Haixu Li, Zhanfeng Cao, Guangcai Yuan, Xue Dong, Guoqiang Wang, Zhijun Lv
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Publication number: 20230379085Abstract: A physical layer retransmission control method is used for retransmission control of a transmission system. The transmission system includes a first transmission terminal, a second transmission terminal and a transmission channel. The first transmission terminal sends downlink data packets to the second transmission terminal through the transmission channel. The second transmission terminal sends retransmission control information to the first transmission terminal through the transmission channel. Each downlink data packet includes a sequence number and an abnormal state field. The sequence numbers in the consecutive downlink data packets are arranged in the order of transmission. The abnormal state field indicates the abnormal state of the data of the first transmission terminal.Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Inventors: Ke LIANG, Yuanlong WANG
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Publication number: 20230342029Abstract: This disclosure provides a memory device, a memory system, and an operation method. The memory device includes a memory array having a plurality of memory blocks and a control circuit coupled to the memory array and used to control the memory array. The control circuit is configured to determine a first average value of threshold voltages of bottom dummy cells in an unused memory block, determine a difference value between the first average value and a first reference value, and judge based on the difference value when bottom dummy cells in the memory block are to be programmed so that the first average value reaches a first threshold.Type: ApplicationFiled: September 8, 2022Publication date: October 26, 2023Inventors: Zhipeng Dong, Ying Huang, Manxi Wang, Hongtao Liu, Ling Chu, Ke Liang
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Publication number: 20230326537Abstract: A memory device includes a memory array including memory blocks, and a control circuit coupled to the memory array. The control circuit is configured to when multi-pass program operations are performed, during a non-last pass program of the memory cells in a first memory sub-block of a first memory block, determine verify loop counts of verify operations after programming the memory cells in the first memory sub-block of the first memory block to one or more first target program states; and when programming the memory cells in a second memory sub-block of the first memory block to the one or more first target program states using the same program and verify conditions as for the first memory sub-block of the first memory block, during the non-last pass program, not perform at least the verify operation corresponding to the last of the verify loop counts.Type: ApplicationFiled: March 17, 2023Publication date: October 12, 2023Inventors: Zhipeng Dong, Ke Liang
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Patent number: 11715523Abstract: In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. The peripheral circuit is configured to program a row of memory cells using a first program voltage and verify the programmed row of memory cells using a verify voltage and a sample voltage smaller than the verify voltage. The peripheral circuit is also configured to obtain a first number of memory cells of the programmed row of memory cells based on the sample voltage. The peripheral circuit is further configured to predict, based on the first number of memory cells and the sample voltage, a second number of memory cells of the programmed row of memory cells that fail to pass the verification.Type: GrantFiled: July 23, 2021Date of Patent: August 1, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Ke Liang, Yueping Li, Chunyuan Hou
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Patent number: 11527292Abstract: In certain aspects, a memory device includes an array of memory cells including a plurality of rows of memory cells, a plurality of word lines respectively coupled to the plurality of rows of memory cells, and a peripheral circuit coupled to the plurality of word lines and configured to perform an erase operation on a selected row of memory cells of the plurality of rows of memory cells. The selected row of memory cells is coupled to a selected word line. To perform the erase operation, the peripheral circuit is configured to discharge an unselected word line coupled to an unselected row of memory cells of the plurality of rows of memory cells from an initial voltage to a discharge voltage in a first time period, and float the unselected word line in a second time period after the first time period.Type: GrantFiled: April 15, 2021Date of Patent: December 13, 2022Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Ke Liang, Chunyuan Hou
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Patent number: 11468954Abstract: A memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, a controller configured to control a read operation on the array of memory cells, and a row decoder coupled to the word lines and the controller and configured to, in the read operation, induce a coupling effect between a select word line and an adjacent unselect word line of the plurality of word lines, and discharge the select word line to a start read level due to at least the coupling effect.Type: GrantFiled: May 25, 2021Date of Patent: October 11, 2022Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Ke Liang, Li Xiang
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Publication number: 20220310169Abstract: In certain aspects, a memory device includes an array of memory cells including a plurality of rows of memory cells, a plurality of word lines respectively coupled to the plurality of rows of memory cells, and a peripheral circuit coupled to the plurality of word lines and configured to perform an erase operation on a selected row of memory cells of the plurality of rows of memory cells. The selected row of memory cells is coupled to a selected word line. To perform the erase operation, the peripheral circuit is configured to discharge an unselected word line coupled to an unselected row of memory cells of the plurality of rows of memory cells from an initial voltage to a discharge voltage in a first time period, and float the unselected word line in a second time period after the first time period.Type: ApplicationFiled: April 15, 2021Publication date: September 29, 2022Inventors: Ke Liang, Chunyuan Hou
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Publication number: 20220301626Abstract: In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. The peripheral circuit is configured to program a row of memory cells using a first program voltage and verify the programmed row of memory cells using a verify voltage and a sample voltage smaller than the verify voltage. The peripheral circuit is also configured to obtain a first number of memory cells of the programmed row of memory cells based on the sample voltage. The peripheral circuit is further configured to predict, based on the first number of memory cells and the sample voltage, a second number of memory cells of the programmed row of memory cells that fail to pass the verification.Type: ApplicationFiled: July 23, 2021Publication date: September 22, 2022Inventors: Ke Liang, Yueping Li, Chunyuan Hou
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Patent number: 11424237Abstract: A memory device includes a first plurality of program lines of a first group, a second plurality of program lines of a second group, and a plurality of address lines. The second plurality of program lines are disposed next to and are parallel to the first plurality of program lines. The plurality of address lines are coupled to the first plurality of program lines and the second plurality of program lines respectively. The plurality of address lines are twisted and are intersected with the first plurality of program lines and the second plurality of program lines in a layout view. At least two adjacent program lines of the first plurality of program lines or the second plurality of program lines have lengths different from each other. A method is also disclosed herein.Type: GrantFiled: July 14, 2020Date of Patent: August 23, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITEDInventors: Yuan Ma, Ke-Liang Shang, Xin-Yong Wang
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Patent number: 11328782Abstract: Memory might have a controller configured to program a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and program the second portion of memory cells in an order from the particular end to the different end. Memory might further have a controller configured to increment first and second read counts in response to performing a read operation on a memory cell of a block of memory cells, reset the first read count in response to performing an erase operation on a first portion of the block of memory cells, and reset the second read count in response to performing an erase operation on the second portion of the block of memory cells.Type: GrantFiled: December 7, 2020Date of Patent: May 10, 2022Assignee: Micron Technology, Inc.Inventors: Ke Liang, Jun Xu
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Publication number: 20210375852Abstract: A memory device includes a first plurality of program lines of a first group, a second plurality of program lines of a second group, and a plurality of address lines. The second plurality of program lines are disposed next to and are parallel to the first plurality of program lines. The plurality of address lines are coupled to the first plurality of program lines and the second plurality of program lines respectively. The plurality of address lines are twisted and are intersected with the first plurality of program lines and the second plurality of program lines in a layout view. At least two adjacent program lines of the first plurality of program lines or the second plurality of program lines have lengths different from each other. A method is also disclosed herein.Type: ApplicationFiled: July 14, 2020Publication date: December 2, 2021Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITEDInventors: Yuan MA, Ke-Liang SHANG, Xin-Yong WANG
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Patent number: 11145362Abstract: A method for programming a memory system including a plurality of memory cells includes performing a first program operation on the plurality of the memory cells. The method also includes identifying a first memory cell and a second set of memory cell from the plurality of memory cells based on threshold voltages of the plurality of memory cells after performing the first program operations. The method further includes performing a second operation on the plurality of the memory cells by applying a first cross voltage to the first memory cell and a second cross voltage to the second memory cell.Type: GrantFiled: January 27, 2021Date of Patent: October 12, 2021Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Ke Liang, Chun Yuan Hou, Qiang Tang
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Publication number: 20210280258Abstract: A memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, a controller configured to control a read operation on the array of memory cells, and a row decoder coupled to the word lines and the controller and configured to, in the read operation, induce a coupling effect between a select word line and an adjacent unselect word line of the plurality of word lines, and discharge the select word line to a start read level due to at least the coupling effect.Type: ApplicationFiled: May 25, 2021Publication date: September 9, 2021Inventors: Ke Liang, Li Xiang