Abstract: Aspects of the invention include systems and methods to obtain meta features of a dataset for training in a deep learning application. A method includes selecting an initial search space that defines a type of deep learning architecture representation that specifies hyperparameters for two or more neural network architectures. The method also includes applying a search strategy to the initial search space. One of the two or more neural network architectures are selected based on a result of an evaluation according to the search strategy. A new search space is generated with new hyperparameters using an evolutionary algorithm and a mutation type that defines one or more changes in the hyperparameters specified by the initial search space, and, based on the mutation type, the new hyperparameters are applied to the one of the two or more neural networks or the search strategy is applied to the new search space.

Abstract: Implementations of the present specification provide a data processing method, apparatus, and device. The method includes: obtaining to-be-detected target data, and obtaining a target probability that the target data corresponds to each candidate user intention, where the target data includes input data of a user in a human-computer interaction process; dividing the target data to obtain a plurality of pieces of subdata, and obtaining, based on a predetermined gradient integration algorithm, a contribution of each piece of subdata to a correspondence between the target data and each candidate user intention; and determining a target user intention corresponding to the target data based on the target probability that the target data corresponds to each candidate user intention and the contribution of each piece of subdata to the correspondence between the target data and each candidate user intention.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to preserve privacy in a user dataset including interface circuitry, machine readable instructions, and programmable circuitry to determine a data usage type for each one of a plurality of user data features in a first dataset, classify the data usage type associated with each user data feature of the plurality of user data feature into a feature category, apply at least one feature engineering mechanism to feature categories of the data usage types of the plurality of user data features, select, based on application of feature engineering, a subset of the plurality of user data features for a feature selection training model, and output a second dataset based on the subset of the plurality of user data for the feature selection training model, the second dataset to include fewer user data features than the first dataset.

Abstract: An optical fiber connector includes a connecting unit, an adapter unit, and an attenuation unit. The adapter unit includes an insertion seat connected removably to a main housing of the connecting unit, and two guide frame bodies located respectively at two opposite sides of the insertion seat in a transverse direction. The insertion seat has two insertion holes spaced apart in the transverse direction and extending in a front-rear direction. Each guide frame body extends in the front-rear direction away from the connecting unit. The attenuation unit includes two attenuation components, two rear ferrules, and two front ferrules. The attenuation components are arranged in the transverse direction and disposed within the main housing. The rear ferrules respectively extend rearwardly from rear ends of the attenuation components into the insertion holes. The front ferrules respectively extend forwardly from front ends of the attenuation components through and outwardly of the main housing.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed that include interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to associate first datapoints of a first feature with a first node, associate second datapoints of a second feature with a second node, construct a graph from the first datapoints and the second datapoints, and perform a comparison of a graph accuracy with a baseline accuracy.

Abstract: Provided is a method for recycling lead iodide and a substrate of a waste perovskite device. The method includes steps as follows: preparing an iodide solution having a set concentration; immersing the waste perovskite device in the iodide solution for dissolution until a perovskite substance of the waste perovskite device is not dissolved, and extracting supernatant; adding water to the supernatant for dilution, and obtaining lead iodide crystals containing a small quantity of impurities; washing the lead iodide crystals containing a small quantity of impurities, adding acid to treat the lead iodide crystals, washing the lead iodide crystals with isopropanol and ether to obtain lead iodide powder, and drying the lead iodide powder to obtain obtaining recycled lead iodide; and cleaning and recycling a substrate generated. The lead iodide is recycled according to Le Chatelier's principle, which achieves safe, environmentally friendly and low-cost recycling.

Abstract: A protector installation device for an electronic device includes a shell and a protector. The shell is provided with an accommodating space, a first mounting end face, and a second mounting end face. The accommodating space is communicated to the second mounting end face of the shell from the first mounting end face of the shell, so that the accommodating space forms a placement opening in the first mounting end face, and the accommodating space forms a mounting opening in the second mounting end face. The placement opening is used for allowing the electronic device to be put into the accommodating space. The protector is arranged on the second mounting end face; and the protector blocks the mounting opening, so that the protector is fitted to a screen of the electronic device in the accommodating space via the mounting opening.

Abstract: The present disclosure relates to a dynamic D flip-flop, a register, a chip, and a data processing apparatus. A dynamic D flip-flop is provided, including: an input terminal, configured to receive input data; an output terminal, configured to provide output data in response to the input data; clock signal terminal(s), configured to receive clock signal(s); a first latch unit, configured to latch the input data from the input terminal and transmit the input data under control of the clock signal(s); and a second latch unit, configured to latch data from the first latch unit and transmit the data latched by the first latch unit under control of the clock signal(s), where the first latch unit and the second latch unit are sequentially connected in series between the input terminal and the output terminal, and where the output terminal is configured to use data from the second latch unit as the output data for outputting.

Abstract: A fiber optic adaptor includes a main shell body and an outer cover. The main shell body has a first end portion and a second end portion. The first end portion defines a first opening and is formed with two engaging grooves. The outer cover is removably disposed on and covering the first end portion, and has a cover body portion, two locking clips, and an identifier portion. The two locking clips protrudes from the cover and respectively engage the engaging grooves. The identifier portion is disposed on the cover body portion. The locking clips are operable to be removed respectively from the engaging grooves. The cover body portion defines a port outer opening, and a port key portion.

Abstract: Circuits and methods for performing a hash algorithm are disclosed. A circuit includes: an input module receiving data; and an operation module calculating a hash value based on the received data. The operation module includes multiple operation stages (0th operation stage, 1st operation stage, up to P-th operation stage, P being a fixed positive integer greater than 1 and less than the number of operation stages in a pipeline structure) arranged in the pipeline structure. Each of the 1st operation stage to P-th operation stage includes: cache registers storing intermediate values of a current operation stage and operating at a first frequency, and extension registers storing extension data of the current operation stage and the extension registers comprising a first set of extension registers operating at the first frequency and a second set of extension registers operating at a second frequency which is 1/N times the first frequency.

Abstract: The present disclosure relates to a circuit for performing a hash algorithm, computing chip, data processing device and method. A circuit includes: operation stages in a pipeline structure each including 0th to 15th expansion registers; expansion data operation logic modules each disposed between two adjacent operation stages including a first operation stage and its subsequent second operation stage, and including a first sub-module configured to compute data in a 0th expansion register of the second operation stage based on data in a 1st expansion register of the first operation stage and a second sub-module configured to compute data in a 15th expansion register of the second operation stage based on data in a 0th expansion register of the first operation stage: data in an (i?1)th expansion register of the second operation stage is data in an ith expansion register of the first operation stage.

Abstract: The fiber optic connector includes a connector head module, a mounting seat, a rear boot, an engaging module and a sheath member. The mounting seat is mounted to a rear end of the connector head module, and includes an external threaded portion. The rear boot is connected to a rear end of the mounting seat. The engaging module is removably coupled to the connector head module. The sheath member includes an internal threaded portion that is formed in an inner surface of the sheath member. When the engaging module is removed from the connector head module, the sheath member can be attachable to the mounting seat with the external threaded portion being threadedly engaged with the external threaded portion of the mounting seat.

Abstract: This disclosure relates to a computing chip, a hashrate board, and a data processing apparatus. The computing chip includes a plurality of operation stages arranged in a pipeline configuration. Each operation stage includes: a first combinational logic circuit occupying a plurality of first cell points adjacent to each other, at least a portion of the first cell points being located in a first incomplete column; one or more second combinational logic circuits each occupying one or more second cell points, at least a portion of the second cell points being located in a second incomplete column; and a plurality of registers each occupying a plurality of third cell points, at least a portion of the third cell points being located in the first incomplete column or the second incomplete column. The first cell points, the second cell points, and third cell points occupy equal areas on the computing chip.

Abstract: A fiber optic adaptor includes a main shell body and an outer cover. The main shell body has a first end portion and a second end portion. The first end portion defines a first opening and is formed with two engaging grooves. The outer cover is removably disposed on and covering the first end portion, and has a cover body portion, two locking clips, and an identifier portion. The two locking clips protrudes from the cover and respectively engage the engaging grooves. The identifier portion is disposed on the cover body portion. The locking clips are operable to be removed respectively from the engaging grooves. The cover body portion defines a port outer opening, and a port key portion.

Abstract: This disclosure relates to a device performing hash algorithm. A hash engine includes an operation module performing a hash operation on a data block and a clock module. The operation module includes operation stages each including registers and a combinational logic module. A digital signal based on the data block is sequentially delivered along the operation stages. Outputs of a first set of registers are coupled to an input of the combinational logic module of the current operation stage. Inputs of a second set of registers are coupled to an output of a combinational logic module of a previous operation stage. A clock signal, provided by the clock module to each operation stage, is sequentially delivered along a multi-stage clock driving circuits of the clock module. For the first and second sets of registers, a delivery direction of the digital signal is the same as that of the clock signal.

Abstract: The present disclosure relates to a circuit for performing a hash algorithm, computing chip, data processing device and method. A circuit includes: operation stages in a pipeline structure each including 0th to 15th expansion registers; expansion data operation logic modules each disposed between two adjacent operation stages including a first operation stage and its subsequent second operation stage, and including a first sub-module configured to compute data in a 0th expansion register of the second operation stage based on data in a 1st expansion register of the first operation stage and a second sub-module configured to compute data in a 15th expansion register of the second operation stage based on data in a 0th expansion register of the first operation stage: data in an (i?1)th expansion register of the second operation stage is data in an ith expansion register of the first operation stage.

Abstract: A fiber optic adapter includes a surrounding wall defining a communication space, two first protruding walls located in the communication space and connected to the surrounding wall, two second protruding walls located in the communication space and connected to the surrounding wall, and an error-proofing protrusion disposed on the surrounding wall, and located in a first key groove between the first protruding walls.

Abstract: This disclosure relates to a computing chip, a hashrate board, and a data processing apparatus. The computing chip includes a plurality of operation stages arranged in a pipeline configuration. Each operation stage includes: a first combinational logic circuit occupying a plurality of first cell points adjacent to each other, at least a portion of the first cell points being located in a first incomplete column; one or more second combinational logic circuits each occupying one or more second cell points, at least a portion of the second cell points being located in a second incomplete column; and a plurality of registers each occupying a plurality of third cell points, at least a portion of the third cell points being located in the first incomplete column or the second incomplete column. The first cell points, the second cell points, and third cell points occupy equal areas on the computing chip.

Abstract: This disclosure relates to a device performing hash algorithm A hash engine includes an operation module performing a hash operation on a data block and a clock module. The operation module includes operation stages each including registers and a combinational logic module. A digital signal based on the data block is sequentially delivered along the operation stages. Outputs of a first set of registers are coupled to an input of the combinational logic module of the current operation. Inputs of a second set of registers are coupled to an output of a combinational logic module of a previous operation stage. A clock signal, provided by the clock module to each operation stage, is sequentially delivered along a multi-stage clock driving circuits of the clock module. For the first and second sets of registers, a delivery direction of the digital signal is the same as that of the clock signal.

Abstract: Circuits and methods for performing a hash algorithm are disclosed. A circuit includes: an input module receiving data; and an operation module calculating a hash value based on the received data. The operation module includes multiple operation stages (0th operation stage, 1st operation stage, up to P-th operation stage, P being a fixed positive integer greater than 1 and less than the number of operation stages in a pipeline structure) arranged in the pipeline structure. Each of the 1st operation stage to P-th operation stage includes: cache registers storing intermediate values of a current operation stage and operating at a first frequency, and extension registers storing extension data of the current operation stage and the extension registers comprising a first set of extension registers operating at the first frequency and a second set of extension registers operating at a second frequency which is 1/N times the first frequency.