Patents by Inventor Ke-Ying Su
Ke-Ying Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111935Abstract: A method of generating an IC layout diagram includes receiving the IC layout diagram including an active region, a gate region extending across the active region from a first active region edge to a second active region edge, and a gate via positioned at a location along the gate region between the first and second edges, configuring a delta resistance network including the first and second edges, a midpoint between the first and second edges, and resistance values based on the location and first and second edges, and performing a simulation based on the delta resistance network.Type: ApplicationFiled: November 27, 2023Publication date: April 4, 2024Inventors: Ke-Ying SU, Ke-Wei SU, Keng-Hua KUO, Lester CHANG
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Patent number: 11907636Abstract: A method of generating an IC layout diagram includes receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region, determining a second gate resistance value based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.Type: GrantFiled: July 8, 2022Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang-Yi Chen, Wen-Hsing Hsieh, Wen-Koi Lai, Keng-Hua Kuo, Kuopei Lu, Lester Chang, Ze-Ming Wu
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Patent number: 11842135Abstract: A method of generating an integrated circuit (IC) layout diagram of an IC device includes receiving the IC layout diagram of the IC device, the IC layout diagram including a gate region having a width across an active region. The width is divided into a plurality of width segments based on a location of a gate via, and a simulation is performed based on the IC layout diagram and including an effective resistance calculated using at least one width segment of the plurality of width segments.Type: GrantFiled: September 24, 2020Date of Patent: December 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ke-Ying Su, Ke-Wei Su, Keng-Hua Kuo, Lester Chang
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Publication number: 20230325575Abstract: A method of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including layout cells, the method including generating the layout diagram including: for a candidate cell amongst the layout cells in the layout diagram, avoiding a discrete calculation of a corresponding parasitic capacitance (PC) description including, within a database which stores predefined cells and corresponding parasitic capacitance (PC) descriptions thereof, searching the database for one amongst the predefined cells (matching predefined cell) that is a substantial match to the candidate cell: and, when a substantial match is found, assigning the PC description of the matching predefined cell to the candidate cell.Type: ApplicationFiled: June 15, 2023Publication date: October 12, 2023Inventors: Ke-Ying SU, Ze-Ming WU, Po-Jui LIN
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Patent number: 11681847Abstract: A method is disclosed for storing and reusing the PC description of layout cells. A database stores predefined cells and PC descriptions that were previously calculated by a 3D field solver. Regarding a candidate cell from the layout diagram, the database is searched for a substantial match amongst the predefined cells. If there is a match, then the stored PC description of the matching predefined cell is assigned to the candidate cell in the layout diagram, which avoids having to make a discrete calculation for the PC description. If there is no match, then the 3D field solver is applied to the candidate cell in order to calculate the PC description of the candidate cell. To facilitate reusing the newly calculated PC description, the candidate cell and the newly calculated PC description are stored in the database as a new predefined cell and its corresponding PC description.Type: GrantFiled: March 11, 2021Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ke-Ying Su, Ze-Ming Wu, Po-Jui Lin
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Publication number: 20220343054Abstract: A method of generating an IC layout diagram includes receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region, determining a second gate resistance value based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.Type: ApplicationFiled: July 8, 2022Publication date: October 27, 2022Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU
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Patent number: 11392749Abstract: A method of generating a netlist of an IC device includes receiving gate region information of the IC device. The gate region information includes a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, a location of a gate via positioned within the active region and along the width, and a first gate resistance value corresponding to the gate region. The method includes determining a second gate resistance value based on the location and the width, and modifying the netlist based on the second gate resistance value.Type: GrantFiled: November 18, 2020Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang-Yi Chen, Wen-Hsing Hsieh, Wen-Koi Lai, Keng-Hua Kuo, KuoPei Lu, Lester Chang, Ze-Ming Wu
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Publication number: 20220147678Abstract: A method for capacitance extraction includes: performing a first capacitance extraction on one or more first regions of a semiconductor layout; performing a second capacitance extraction on one or more second regions of the semiconductor layout, a resolution of the second capacitance extraction being less than a resolution of the first capacitance extraction; constructing a netlist for the semiconductor layout based on results of the first capacitance extraction and of the second capacitance extraction; and modifying the semiconductor layout based on the netlist. The modified semiconductor layout is used to fabricate an integrated circuit.Type: ApplicationFiled: June 30, 2021Publication date: May 12, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo Fu LEE, Ching Yang YEN, Ke-Ying SU, Chau-Wen WEI
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Publication number: 20220012401Abstract: A method is disclosed for storing and reusing the PC description of layout cells. A database stores predefined cells and PC descriptions that were previously calculated by a 3D field solver. Regarding a candidate cell from the layout diagram, the database is searched for a substantial match amongst the predefined cells. . If there is a match, then the stored PC description of the matching predefined cell is assigned to the candidate cell in the layout diagram, which avoids having to make a discrete calculation for the PC description. If there is no match, then the 3D field solver is applied to the candidate cell in order to calculate the PC description of the candidate cell. To facilitate reusing the newly calculated PC description, the candidate cell and the newly calculated PC description are stored in the database as a new predefined cell and its corresponding PC description.Type: ApplicationFiled: March 11, 2021Publication date: January 13, 2022Inventors: Ke-Ying SU, Ze-Ming WU, Po-Jui LIN
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Publication number: 20210073454Abstract: A method of generating a netlist of an IC device includes receiving gate region information of the IC device. The gate region information includes a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, a location of a gate via positioned within the active region and along the width, and a first gate resistance value corresponding to the gate region. The method includes determining a second gate resistance value based on the location and the width, and modifying the netlist based on the second gate resistance value.Type: ApplicationFiled: November 18, 2020Publication date: March 11, 2021Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU
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Patent number: 10922464Abstract: Fabricating a first semiconductor device cell using a first process based on a first process parameter or material comprises extracting semiconductor device parameters from the first process parameters to obtain extracted semiconductor device parameters of a first semiconductor device cell. The fabrication process includes training an artificial intelligence to obtain a predictive artificial intelligence using training data as input, the training data comprising the extracted semiconductor device cell parameters and the first process parameter or material. A proposed process modification is provided to the predictive artificial intelligence to generate a predicted cell delay by the predictive artificial intelligence. The predicted cell delay is evaluated against a cell delay threshold. When the predicted cell delay satisfies the cell delay threshold, a new semiconductor device cell is fabricated using a modified process incorporating the proposed process modification.Type: GrantFiled: December 10, 2019Date of Patent: February 16, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hui-I Wu, Ke-Ying Su, Wan-Ting Lo, Niranjan Vepuri, Hsiang-Ho Chang
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Publication number: 20210019467Abstract: A method of generating an integrated circuit (IC) layout diagram of an IC device includes receiving the IC layout diagram of the IC device, the IC layout diagram including a gate region having a width across an active region. The width is divided into a plurality of width segments based on a location of a gate via, and a simulation is performed based on the IC layout diagram and including an effective resistance calculated using at least one width segment of the plurality of width segments.Type: ApplicationFiled: September 24, 2020Publication date: January 21, 2021Inventors: Ke-Ying SU, Ke-Wei SU, Keng-Hua KUO, Lester CHANG
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Patent number: 10846456Abstract: A method of generating a netlist of an IC device includes extracting dimensions of a gate region of the IC device, the dimensions including a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, and a distance from a first end of the width to a gate via positioned along the width. A first gate resistance value corresponding to the gate region is received, a second gate resistance value is determined based on the distance and the width, and the netlist is updated based on the first and second gate resistance values.Type: GrantFiled: April 19, 2019Date of Patent: November 24, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang-Yi Chen, Wen-Hsing Hsieh, Wen-Koi Lai, Keng-Hua Kuo, KuoPei Lu, Lester Chang, Ze-Ming Wu
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Patent number: 10796059Abstract: A method of generating an integrated circuit (IC) layout diagram of an IC device includes receiving a layout diagram of the IC device, the IC layout diagram including a gate region having a width across an active region, and a gate via positioned at a location along the width. The location is used to divide the width into a plurality of width segments, an effective resistance of the gate region is calculated based on the plurality of width segments, and the effective resistance is used to determine whether the IC layout diagram complies with a design specification.Type: GrantFiled: March 6, 2019Date of Patent: October 6, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ke-Ying Su, Ke-Wei Su, Keng-Hua Kuo, Lester Chang
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Publication number: 20200110913Abstract: Fabricating a first semiconductor device cell using a first process based on a first process parameter or material comprises extracting semiconductor device parameters from the first process parameters to obtain extracted semiconductor device parameters of a first semiconductor device cell. The fabrication process includes training an artificial intelligence to obtain a predictive artificial intelligence using training data as input, the training data comprising the extracted semiconductor device cell parameters and the first process parameter or material. A proposed process modification is provided to the predictive artificial intelligence to generate a predicted cell delay by the predictive artificial intelligence. The predicted cell delay is evaluated against a cell delay threshold. When the predicted cell delay satisfies the cell delay threshold, a new semiconductor device cell is fabricated using a modified process incorporating the proposed process modification.Type: ApplicationFiled: December 10, 2019Publication date: April 9, 2020Inventors: Hui-I Wu, Ke-Ying Su, Wan-Ting Lo, Niranjan Vepuri, Hsiang-Ho Chang
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Patent number: 10515172Abstract: Fabricating a first semiconductor device cell using a first process based on a first process parameter or material comprises extracting semiconductor device parameters from the first process parameters to obtain extracted semiconductor device parameters of a first semiconductor device cell. The fabrication process includes training an artificial intelligence to obtain a predictive artificial intelligence using training data as input, the training data comprising the extracted semiconductor device cell parameters and the first process parameter or material. A proposed process modification is provided to the predictive artificial intelligence to generate a predicted cell delay by the predictive artificial intelligence. The predicted cell delay is evaluated against a cell delay threshold. When the predicted cell delay satisfies the cell delay threshold, a new semiconductor device cell is fabricated using a modified process incorporating the proposed process modification.Type: GrantFiled: October 15, 2018Date of Patent: December 24, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hui-I Wu, Ke-Ying Su, Wan-Ting Lo, Niranjan Vepuri, Hsiang-Ho Chang
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Publication number: 20190340328Abstract: A method of generating a netlist of an IC device includes extracting dimensions of a gate region of the IC device, the dimensions including a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, and a distance from a first end of the width to a gate via positioned along the width. A first gate resistance value corresponding to the gate region is received, a second gate resistance value is determined based on the distance and the width, and the netlist is updated based on the first and second gate resistance values.Type: ApplicationFiled: April 19, 2019Publication date: November 7, 2019Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU
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Publication number: 20190294750Abstract: A method of generating a layout diagram of an IC device includes receiving a layout diagram of the IC device, the IC layout diagram including a gate region having a width across an active region, and a gate via positioned at a location along the width. The location is used to divide the width into a plurality of width segments, an effective resistance of the gate region is calculated based on the plurality of width segments, and the effective resistance is used to determine whether the IC layout diagram complies with a design specification.Type: ApplicationFiled: March 6, 2019Publication date: September 26, 2019Inventors: Ke-Ying SU, Ke-Wei SU, Keng-Hua KUO, Lester CHANG
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Publication number: 20190121928Abstract: Fabricating a first semiconductor device cell using a first process based on a first process parameter or material comprises extracting semiconductor device parameters from the first process parameters to obtain extracted semiconductor device parameters of a first semiconductor device cell. The fabrication process includes training an artificial intelligence to obtain a predictive artificial intelligence using training data as input, the training data comprising the extracted semiconductor device cell parameters and the first process parameter or material. A proposed process modification is provided to the predictive artificial intelligence to generate a predicted cell delay by the predictive artificial intelligence. The predicted cell delay is evaluated against a cell delay threshold. When the predicted cell delay satisfies the cell delay threshold, a new semiconductor device cell is fabricated using a modified process incorporating the proposed process modification.Type: ApplicationFiled: October 15, 2018Publication date: April 25, 2019Inventors: Hui-I Wu, Ke-Ying Su, Wan-Ting Lo, Niranjan Vepuri, Hsiang-Ho Chang
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Patent number: 10140407Abstract: A method performed at least partially by a processor includes performing an air gap insertion process. The air gap insertion process includes sorting a plurality of nets of a layout of an integrated circuit in an order, and inserting, in accordance with the sorted order of the plurality of nets, air gap patterns adjacent to the plurality of nets. The method further includes generating a modified layout of the integrated circuit. The modified layout includes the plurality of nets and the inserted air gap patterns.Type: GrantFiled: November 26, 2014Date of Patent: November 27, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Ming Ho, Adari Rama Bhadra Rao, Meng-Kai Hsu, Kuang-Hung Chang, Ke-Ying Su, Wen-Hao Chen, Hsien-Hsin Sean Lee