Patents by Inventor Kedar Mangrulkar

Kedar Mangrulkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Accurate on-die temperature measurement using remote sensing
    Patent number: 7512514
    Abstract: An embodiment of the present invention is a technique for thermal sensing. A sensing structure generates a response according to a local temperature at a first location on a die. A sensor core coupled to the sensing structure via routing lines to provide a measurement of the local temperature from the response. The sensor core is located at a second location remote to the first location and is powered by an analog supply voltage source located in a vicinity of the second location.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: March 31, 2009
    Assignee: Intel Corporation
    Inventors: David Duarte, George Geannopoulos, Usman Mughal, Venkatesh Prasanna, Kedar Mangrulkar, Mathew Nazareth
  • Accurate on-die temperature measurement using remote sensing
    Publication number: 20080082282
    Abstract: An embodiment of the present invention is a technique for thermal sensing. A sensing structure generates a response according to a local temperature at a first location on a die. A sensor core coupled to the sensing structure via routing lines to provide a measurement of the local temperature from the response. The sensor core is located at a second location remote to the first location and is powered by an analog supply voltage source located in a vicinity of the second location.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Inventors: David Duarte, George Geannopoulos, Usman Mughal, Venkatesh Prasanna, Kedar Mangrulkar, Mathew Nazareth
  • Maintaining processor execution during frequency transitioning
    Patent number: 7210054
    Abstract: An embodiment of the present invention includes a standby clock generator and a selector. The standby clock generator generates a standby clock synchronous to a core clock. The core clock is generated by a core clock generator during a normal operation mode. The core clock generator stops the core clock during a frequency transition. The selector generates a processor clock from the standby clock during the frequency transition from the normal operation mode according to a selector control signal.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: April 24, 2007
    Assignee: Intel Corporation
    Inventors: Sanjeev Jahagirdar, Islam Derhalli, Varghese George, Kedar Mangrulkar, Mathew Nazareth
  • Method and apparatus for accurate on-die temperature measurement
    Patent number: 7149645
    Abstract: A device and method for continually monitoring multiple thermal sensors located at hotspots across a processor. The sensors are connected to a sensor cycling and selection block located at a periphery of the die. The output from the sensor selection block is converted into a digital temperature code. Based on the digital temperature code, thermal events trigger various thermal controls. The thermal event triggers may be software-programmable, providing flexible temperature management.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: December 12, 2006
    Assignee: Intel Corporation
    Inventors: Kedar Mangrulkar, Sanjeev Jahagirdar, Varghese George, Venkatesh Prasanna, Inder Sodhi
  • METHOD AND APPARATUS FOR ACCURATE ON-DIE TEMPERATURE MEASUREMENT
    Publication number: 20060161373
    Abstract: A device and method for continually monitoring multiple thermal sensors located at hotspots across a processor. The sensors are connected to a sensor cycling and selection block located at a periphery of the die. The output from the sensor selection block is converted into a digital temperature code. Based on the digital temperature code, thermal events trigger various thermal controls. The thermal event triggers may be software-programmable, providing flexible temperature management.
    Type: Application
    Filed: December 30, 2004
    Publication date: July 20, 2006
    Applicant: Intel Corporation
    Inventors: Kedar Mangrulkar, Sanjeev Jahagirdar, Varghese George, Venkatesh Prasanna, Inder Sodhi
  • Circuits and methods for alignment of signals in integrated circuits
    Patent number: 6891417
    Abstract: Circuits and methods align an internal signal with an external signal. A phase lock loop network receives the external signal to generate phase lock loop signals. A programmable ratio decoder provides a code. An alignment unit generates the internal signal based on at least one of the phase lock loop signals. The alignment unit aligns internal signal with the external signal based on the code.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: May 10, 2005
    Assignee: Intel Corporation
    Inventors: Tanveer R Khondker, Vijay Vuppaladadium, Inder Sodhi, Venkatesh Prasanna, Kedar Mangrulkar, Miguel Corvacho, Nakul Arora
  • CIRCUITS AND METHODS FOR ALIGNMENT OF SIGNALS IN INTEGRATED CIRCUITS
    Publication number: 20050001664
    Abstract: Circuits and methods align an internal signal with an external signal. A phase lock loop network receives the external signal to generate phase lock loop signals. A programmable ratio decoder provides a code. An alignment unit generates the internal signal based on at least one of the phase lock loop signals. The alignment unit aligns internal signal with the external signal based on the code.
    Type: Application
    Filed: July 2, 2003
    Publication date: January 6, 2005
    Inventors: Tanveer Khondker, Vijay Vuppaladadium, Inder Sodhi, Venkatesh Prasanna, Kedar Mangrulkar, Miguel Corvacho, Nakul Arora
  • Maintaining processor execution during frequency transitioning
    Publication number: 20030237012
    Abstract: An embodiment of the present invention includes a standby clock generator and a selector. The standby clock generator generates a standby clock synchronous to a core clock. The core clock is generated by a core clock generator during a normal operation mode. The core clock generator stops the core clock during a frequency transition. The selector generates a processor clock from the standby clock during the frequency transition from the normal operation mode according to a selector control signal.
    Type: Application
    Filed: June 25, 2002
    Publication date: December 25, 2003
    Inventors: Sanjeev Jahagirdar, Islam Derhalli, Varghese George, Kedar Mangrulkar, Mathew Nazareth
  • Method and apparatus for low voltage sensing in flash memories
    Patent number: 6366497
    Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a column load component and a current mirror coupled in parallel with the column load component. The column load component is capable of being coupled to a FLASH cell and a sense amplifier.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: April 2, 2002
    Assignee: Intel Corporation
    Inventors: Sandeep Guliani, Chaitanya Rajguru, Kedar Mangrulkar