Abstract: An example of the present invention provides a metal composite catalyst for ammonia decomposition and hydrogen production including a carrier; and Ni metal particles dispersed on a surface of the carrier or inside a pore, in which a content of the Ni metal particle is 15 to 70 parts by weight with reference to 100 parts by weight of the metal composite catalyst, and a diameter of the Ni metal particle is 60 nm or less. More specifically, the metal composite catalyst according to an example of the present invention is manufactured by an ultrasonic method, includes an aging step, and exhibits high efficiency and economy in ammonia decomposition and hydrogen production processes.

Abstract: A nonvolatile memory device includes: a memory cell array including three or more planes; a first clock generator generating a first clock signal having a first period; a second clock generator generating a second clock signal having a second period that varies with the temperature; a plurality of clock switching controllers outputting one of the first and second clock signals as a reference clock signal; a control logic including a plurality of bitline shutoff generators, which output a plurality of bitline shutoff signals based on the reference clock signal; and a plurality of page buffers connecting bitlines of the planes and data latch nodes in accordance with the bitline shutoff signals.

Abstract: An operating method of a nonvolatile memory device including a page buffer array in which a plurality of page buffers are arranged in a matrix form includes counting fail bits stored in the page buffers included in first columns determined based on an operation mode from among a plurality of columns of the page buffer array, and determining whether or not a program has passed with respect to memory cells to which the page buffer array is connected, based on a count result corresponding to a number of the fail bits and a reference count determined based on the operation mode.

Abstract: A non-volatile memory includes a page buffer array in which page buffers are arranged in a matrix form. A method of operating the non-volatile memory includes selecting columns from among multiple columns of the page buffer array, and counting fail bits stored in page buffers included in the selected columns.

Abstract: An operating method of a nonvolatile memory device including a page buffer array in which a plurality of page buffers are arranged in a matrix form includes counting fail bits stored in the page buffers included in first columns determined based on an operation mode from among a plurality of columns of the page buffer array, and determining whether or not a program has passed with respect to memory cells to which the page buffer array is connected, based on a count result corresponding to a number of the fail bits and a reference count determined based on the operation mode.

Abstract: A nonvolatile memory device includes memory blocks that each include cell strings formed vertically on a substrate. The cell strings are coupled to a plurality of bit-lines. The cell strings each include memory cells connected to a string selection transistor. A method of operating the nonvolatile memory device includes performing an erase operation on a first memory block of the memory blocks in response to an erase command, performing an erase verification operation on the memory cells of the first memory block, performing a first sensing operation on the string selection transistors of each of the cell strings coupled to at least some bit-lines of the first memory block, and determining whether the first memory block is a fail block at least based on a result of the first sensing operation. The first sensing operation is based on a first sensing scheme selected among a plurality of sensing schemes.

Abstract: A non-volatile memory includes a page buffer array in which page buffers are arranged in a matrix form. A method of operating the non-volatile memory includes selecting columns from among multiple columns of the page buffer array, and counting fail bits stored in page buffers included in the selected columns.

Abstract: A nonvolatile memory device includes memory blocks that each include cell strings formed vertically on a substrate. The cell strings are coupled to a plurality of bit-lines. The cell strings each include memory cells connected to a string selection transistor. A method of operating the nonvolatile memory device includes performing an erase operation on a first memory block of the memory blocks in response to an erase command, performing an erase verification operation on the memory cells of the first memory block, performing a first sensing operation on the string selection transistors of each of the cell strings coupled to at least some bit-lines of the first memory block, and determining whether the first memory block is a fail block at least based on a result of the first sensing operation. The first sensing operation is based on a first sensing scheme selected among a plurality of sensing schemes.

Abstract: A flash memory device includes a program data buffer configured to buffer program data to be programmed in a memory cell array, and a verify data buffer configured to compare verify data to confirm whether the program data is accurately programmed in the memory cell array, wherein at least a portion of the verify data buffer is selectively enabled as a verify data buffer or a program data buffer responsive to a buffer control signal.

Abstract: In one aspect, a program method is provided for a flash memory device including a plurality of memory cells each being programmed in one of a plurality of data states. The program method of this aspect includes programming selected memory cells in a first data state, verifying a result of the programming, successively programming selected memory cells in at least two or more data states corresponding to threshold voltages which are lower than a threshold voltage corresponding to the first data state, and verifying results of the successive programming.

Abstract: A method for programming a flash memory device is provided, where the flash memory device includes a plurality of memory cells, and where a threshold voltage of each of the memory cells is programmable in any one of plural corresponding data states. The method includes programming selected memory cells in a first data state, verifying a result of the programming, successively programming selected memory cells in at least two or more data states corresponding to threshold voltages which are lower than a corresponding threshold voltage of the first data state, and verifying results of the successive programming.

Abstract: A method of driving a non-volatile memory device includes programming a plurality of memory cells based on a first data copied from a program data buffer to a verification data buffer, verifying the memory cells by overwriting a result of the verification of the programmed memory cells to a verification data buffer, and re-verifying the memory cells by repeating the programming and verifying operations at least once with respect to the memory cells that were successfully verified, based on the verification result written to the verification data buffer.

Abstract: A flash memory device includes a program data buffer configured to buffer program data to be programmed in a memory cell array, and a verify data buffer configured to compare verify data to confirm whether the program data is accurately programmed in the memory cell array, wherein at least a portion of the verify data buffer is selectively enabled as a verify data buffer or a program data buffer responsive to a buffer control signal.

Abstract: A method of driving a non-volatile memory device includes programming a plurality of memory cells based on a first data copied from a program data buffer to a verification data buffer, verifying the memory cells by overwriting a result of the verification of the programmed memory cells to a verification data buffer, and re-verifying the memory cells by repeating the programming and verifying operations at least once with respect to the memory cells that were successfully verified, based on the verification result written to the verification data buffer.

Abstract: In one aspect, a program method is provided for a flash memory device including a plurality of memory cells each being programmed in one of a plurality of data states. The program method of this aspect includes programming selected memory cells in a first data state, verifying a result of the programming, successively programming selected memory cells in at least two or more data states corresponding to threshold voltages which are lower than a threshold voltage corresponding to the first data state, and verifying results of the successive programming.

Abstract: A method for programming a flash memory device is provided, where the flash memory device includes a plurality of memory cells, and where a threshold voltage of each of the memory cells is programmable in any one of plural corresponding data states.