Abstract: A self-bootstrapping device for sufficiently bootstrapping a bias applied to the gate of a MOS transistor included in the decoder of a semiconductor memory device requiring a high integration degree so that the MOS transistor can transmit the potential from its drain to its source. The self-bootstrapping device includes a first NMOS transistor for a signal transmission, and a second NMOS transistor connected between the gate of the first NMOS transistor and an address decoder circuit, the second NMOS transistor being applied at its gate with a source voltage, wherein the second NMOS transistor comprises a first diffusion region formed at a required portion of a semiconductor substrate, a second diffusion region formed around the first diffusion region while being spaced apart from the first diffusion region by a desired distance, and a gate electrode formed on the semiconductor substrate between the first and second diffusion regions.

Abstract: A power consumption saving apparatus for semiconductor memory devices such as DRAM's, which is configured to preferentially latch a clock signal and a chip selection signal over other input command signals so that latch circuits for latching the input command signals are controlled in accordance with the clock signal and chip selection signal, thereby saving power consumption occurring in input latches not selected. The apparatus includes an input latch as a latch control circuit for preferentially latching a clock signal and a chip selection signal and outputting the latched signals as a control signal for controlling latch circuits.

Abstract: A method for driving word lines in a semiconductor memory device. A main row decoder generates a word line enable signal in s response to one part of address signal bits and a sub row decoder generates a word line boosting signal in response to the other part of the address signal bits. A bootstrap transistor transfers the word line enable signal from the main row decoder to a bootstrap node in response to a specific voltage. A high level voltage transfer transistor transfers the word line boosting signal from the sub row decoder to a corresponding one of the word lines in response to a voltage at the bootstrap node. After the word line enable signal from the main row decoder makes a low to high transition in level, the word line boosting signal from the sub row decoder is changed from a ground voltage level to a high voltage level to drive the corresponding word line. Then, the specific voltage is changed from the present level to the lower level.

Abstract: A word line driver in a semiconductor memory device. The driver has first to (2.sup.m-n)th middle decoding units for commonly inputting an address signal of n bit and for outputting metal control signals by 2.sup.n so as to selectively drive 2.sup.m word lines by dividing them by 2.sup.n ; a main decoding unit for selectively driving the first to (m-n)bits th middle decoding units by an address signal of (m-n) bits; and first to (2.sup.m-n)th sub decoding units for commonly inputting a high voltage via a metal power line, and after coupled with 2.sup.n word lines of the 2.sup.m word lines of the cell array block, for selectively applying the high voltage to the 2.sup.n word lines to selectively drive them according to logic signals of 2.sup.n metal control lines, the first to (2.sup.m-n)th sub decoding units being coupled with the first to (2.sup.m-n)th middle decoding units and the 2.sup.n metal control lines, respectively.

Abstract: A high-speed predecoding address counter circuit comprising at least three tetrad counters connected in series, each for inputting an external 4-bit address decoding signal in response to a set signal and cyclically shifting a logic signal with a specific logic value at its four output terminals in response to a clock signal, a first clock switching unit responsive to a logical value of a most significant bit of an output signal from a lowest-order one of the at least three tetrad counters, for transferring the clock signal to a higher-order one of at least three tetrad counters, at least one logic unit for detecting whether both most significant bits of output signals from at least two lower-order ones of the at least three tetrad counters have the specific logic value, and at least one second clock switching unit connected between at least one logic unit and at least one of the at least three tetrad counters other than the at least two lower-order tetrad counters, for switching the clock signal to the at le

Abstract: A circuit and a method for securing a write recovery operation in a semiconductor memory device. The write recovery security circuit comprises an external signal output unit for outputting an external signal in response to a pulse signal, a external enable signal and a write recovery signal, an external signal latch unit for performing a latch operation in response to the pulse signal, the external enable signal and the write recovery signal to latch an inverted one of the external signal from the external signal output unit while a write recovery operation is performed, and a pulse generator for supplying the pulse signal to the external signal output unit and the external signal latch unit in response to the write recovery signal and transferring the inverted external signal from the external signal output unit to the external signal latch unit in response to the pulse signal.