Abstract: A device for effectively and economically receiving a packet by eliminating temporary memory and a memory controller. The apparatus includes an inspection logic circuit for inspecting data units as soon as they arrive in order to find an error included in the packet and generating control signals according to a result of inspecting a data unit; a multiplexer for receiving data units and distributing the received data units as soon as the data units have arrived; and FIFO memories for receiving the data unit, storing the data unit in a corresponding one of FIFO memories and either deleting or completing storing data units according to the control signals from the inspection logic circuit. The present invention can reduce manufacturing cost of the device by eliminating a temporary memory and a memory controller for the temporary memory and can also reduce processing time.

Abstract: The present invention is a data transfer protocol control system with a host bus interface that includes a transmitting/receiving command DMA, a transmitting data DMA and a receiving data DMA for controlling data transfer protocol with a host bus interface considering characteristic, usage frequency, simultaneous processing functions of the command DMA and the data DMAs. A host interface bus is efficiently used and bus usage ratio is distributed properly to support transfer flow properly and improve the entire system performance.

Abstract: In a first-in first-out memory circuit using a standard cell library memory, a memory block includes N number of memories (N>1). A read pointer designates read addresses of the N number of memories. A write pointer designates write addresses of the N number of memories. A memory controller selects one from the N number of memories based on the read/write addresses, generates n number of read/write clock signals by demultiplying a clock signal by n (n=N, n>1) and sends the n number of read/write clock signals having a 1/n cycle difference to the N number of memories thereby inputting/outputting data.

Abstract: The present invention is a data transfer protocol control system with a host bus interface that includes a transmitting/receiving command DMA, a transmitting data DMA and a receiving data DMA for controlling data transfer protocol with a host bus interface considering characteristic, usage frequency, simultaneous processing functions of the command DMA and the data DMAs. A host interface bus is efficiently used and bus usage ratio is distributed properly to support transfer flow properly and improve the entire system performance.

Abstract: The present invention relates to a radial basis function classifier generating system and method to classify gene expression pattern appearing on micro-array for functional property. In the present invention, the ‘representation coverage’ to be represented by classifier and the ‘representation precision’, instead of various variables, are set to be input variables and other variables required to generate classifier are automatically determined based on the given values of the input variables. Developer's selection of the values of variables is minimized and the unnecessary trial-and-errors are reduced. Developers understand easily meaning of such input variables and can predict the result of the selection of variables. Accordingly, the trial-and-errors due to meaningless selection of the values of the variables are reduced, so the classifier generation process can be optimized.

Abstract: An apparatus for effectively and economically receiving packet by eliminating temporal memory and controller is disclosed. The apparatus includes; an inspection logic circuit for inspecting data units as soon as arrived in order to find error included in the packet and generating control signals according to a result of inspecting data unit; a multiplexer for receiving data units and distributing the received data units as soon as the data units are arrived; and a plurality of FIFO memories for receiving the data unit, storing the data unit in corresponding one of FIFO memories and deleting or completing to store data units according to the control signals from the inspection logic circuit. The present invention can reduce manufacturing cost of the apparatus by eliminating a temporal memory and a memory controller for the temporal memory and can also reduce a processing time.

Abstract: In a first-in first-out memory circuit using a standard cell library memory, a memory block includes N number of memories (N>1). A read pointer designates read addresses of the N number of memories. A write pointer designates write addresses of the N number of memories. A memory controller selects one from the N number of memories based on the read/write addresses, generates n number of read/write clock signals by demultiplying a clock signal by n (n=N, n>1) and sends the n number of read/write clock signals having a 1/n cycle difference to the N number of memories thereby inputting/outputting data.

Abstract: A routing switch for constructing an interconnection network of a parallel processing computer is disclosed. A purpose of the present invention is to provide a crossbar routing switch for a hierarchical interconnection network which has an expandability of a data length and an expandability of a hierarchical structure. The crossbar routing switch for a hierarchical interconnection network in accordance with the present invention comprises a predetermined number of input control units for controlling one input port to perform the manipulation of input data; a crossbar core unit for analyzing a data transmission request by the input control unit and outputting the corresponding data; and a predetermined number of output control unit for controlling one output port and receiving the output data from the crossbar core unit to output it to the output port.

Abstract: The present invention relates to a hierarchical crossbar inter-connection network for a cluster-based parallel processing computer. A crossbar network is composed of the "n" number of crossbar switches which is byte sliced, eight links for connecting eight nodes, and two links for connecting other clusters. In addition, one low-level cluster is formed by connecting a maximum of eight processing nodes between the two crossbar networks, and one high-level cluster is formed with a maximum of eight low-level clusters and the four crossbar networks. Moreover, one next high-level clusters formed with a maximum of eight high-level clusters and the eight crossbar networks for scalability.

Abstract: The present invention relates to a message-passing computer system and a packet-switched interconnection network. The message transfer apparatus in a packet-switched interconnection network includes a message send controller controlling a send procedure in which messages requested by a processor are sent via an output port, and a timer enabled by an output signal of the message send controller and generating a timeout signal. A buffer unit is connected to the message send controller and is composed of a message buffer having four buffers and a data buffer. A local bus controller connects the message send controller and the buffer unit to the local bus and controls a transfer request and a transfer response to the local bus. An output port controller connected to both the message send controller and the buffer unit controls the output port which sends a packet to an interconnection network.

Abstract: A VRAM-based parity engine for use in a disk array controller is disclosed, in which the parity arithmetic operation is carried out in a fast and effective manner, thereby improving the performance of the RAID system. Particularly, the parity data arithmetic operation is not resorted to a processor, but to a VRAM, thereby realizing a high speed operation. In the disk array controller, a VRAM (video RAM) is used, in such a manner that the reading, updating and writing are made to be overlapped during the arithmetic operation, thereby promoting the speed of the arithmetic. Therefore, a relatively large capacity memory can be formed compared with the conventional SRAM, and therefore, a temporary buffer memory within the parity engine is used as a parity cache, thereby doubling the performance.

Abstract: The present invention discloses a method for controlling a message send in a packet-switched interconnection network, which incorporates a message send controller supporting an efficient message send and a dedicated hardware capable of maximizing a message send rate, taking the structural characteristics of the message-passing parallel computer system method into maximum considerations, thereby minimizing software and hardware overhead in sending a message and being capable of selecting a message send method in accordance with the message characteristics.