Patents by Inventor Keen Zhang

Keen Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and memory device including conductive lines and contacts, and methods of forming an apparatus including conductive lines and contacts
    Patent number: 11990367
    Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: May 21, 2024
    Inventors: Xiaosong Zhang, Yongjun J. Hu, David A. Kewley, Md Zahid Hossain, Michael J. Irwin, Daniel Billingsley, Suresh Ramarajan, Robert J. Hanson, Biow Hiem Ong, Keen Wah Chow
  • Interconnect structure and fabricating method thereof
    Patent number: 10332839
    Abstract: An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and exposes the at least one UTM layer. A stress of the first dielectric layer is ?150 Mpa to ?500 Mpa. The at least one pad metal layer is disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: June 25, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Keen Zhang, Ji Feng, De-Jin Kong, Yun-Fei Li, Guo-Hai Zhang, Ching-Hwa Tey, Jing Feng
  • INTERCONNECT STRUCTURE AND FABRICATING METHOD THEREOF
    Publication number: 20180197819
    Abstract: An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and exposes the at least one UTM layer. A stress of the first dielectric layer is ?150 Mpa to ?500 Mpa. The at least one pad metal layer is disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.
    Type: Application
    Filed: January 6, 2017
    Publication date: July 12, 2018
    Applicant: United Microelectronics Corp.
    Inventors: Keen Zhang, Ji Feng, De-Jin Kong, Yun-Fei Li, Guo-Hai Zhang, Ching-Hwa Tey, Jing Feng