Patents by Inventor Kei Hayasaki

Kei Hayasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020170907
    Abstract: A heating apparatus for performing heat treatment on a wafer applied with a resist before or after exposure includes a heating plate for heating a wafer which is placed on the heating plate, a light intensity detecting apparatus for irradiating light on the wafer to detect intensity of reflected light from the resist on the wafer, and a control section for controlling heating performed by the heating plate on the basis of the detected intensity of reflected light so that heating amount applied to a plurality of wafers becomes constant. Accordingly, the heating amount of the wafer can be controlled to be constant and variations in dimension of resist patterns can be reduced.
    Type: Application
    Filed: July 8, 2002
    Publication date: November 21, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kei Hayasaki, Shinichi Ito, Kenji Kawano
  • Publication number: 20020155391
    Abstract: There is disclosed, as an aspect, a method of forming a pattern which comprising coating a photosensitive resist film on a surface of substrate, subjecting the photosensitive resist film to an exposure process, coating an oxidizing liquid having an oxidative effect on a surface of the photosensitive resist film that has been subjected to the exposure process to thereby perform a pretreatment wherein the surface of the resist film is caused to oxidize by the oxidizing liquid to form an oxide layer thereon, feeding a developing solution to the photosensitive resist film whose surface has been oxidized to thereby perform a development of the resist film, and feeding a rinsing solution to a surface of the substrate to wash the substrate.
    Type: Application
    Filed: February 15, 2002
    Publication date: October 24, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Riichiro Takahashi, Kei Hayasaki, Shinichi Ito
  • Publication number: 20020123011
    Abstract: A heating apparatus for a substrate to be processed with a coating film has a chamber with an inner space, a heating plate heating the substrate to be processed in the inner space, and a partition member. The heating plate has a support surface which supports the substrate to be processed within the chamber. The partition member is arranged in the chamber so as to face the support surface. The partition member partitions the inner space into first and second spaces, and has a plurality of pores which allow the first and second spaces to communicate with each other. The support surface of the heating plate is set in the first space. An air stream formation mechanism forming an air stream is arranged in the second space. This mechanism discharges a substance evaporated from the photoresist film.
    Type: Application
    Filed: December 26, 2001
    Publication date: September 5, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenji Kawano, Shinichi Ito, Eishi Shiobara, Daisuke Kawamura, Kei Hayasaki
  • Patent number: 6441351
    Abstract: A heating apparatus for performing heat treatment on a wafer applied with a resist before or after exposure includes a heating plate for heating a wafer which is placed on the heating plate, a light intensity detecting apparatus for irradiating light on the wafer to detect intensity of reflected light from the resist on the wafer, and a control section for controlling heating performed by the heating plate on the basis of the detected intensity of reflected light so that heating amount applied to a plurality of wafers becomes constant. Accordingly, the heating amount of the wafer can be controlled to be constant and variations in dimension of resist patterns can be reduced.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: August 27, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Hayasaki, Shinichi Ito, Kenji Kawano
  • Patent number: 6423977
    Abstract: A pattern size evaluation apparatus comprising an illumination optical system for projecting parallel light rays of a predetermined wavelength on a monitoring area formed on an object, the monitoring area being formed at a position different from a device pattern formed on the object, a light intensity detection optical system for detecting diffracted light from the monitoring area, and a device pattern size evaluation section for evaluating a size of the device pattern based on an intensity of diffracted light from the monitoring area.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: July 23, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Hayasaki, Shinichi Ito, Kenji Kawano, Soichi Inoue, Katsuya Okumura
  • Publication number: 20020015904
    Abstract: In the light exposure step of the device pattern, the monitor region is exposed to light together with the device region for every chip, and chip {circle over (4)} within the wafer, the chip {circle over (4)} having the focus conditions in the light exposure step close to a set value and having an average value of the dose, is extracted after the light exposure of the device pattern and before the developing treatment. The monitor region arranged within the extracted chip {circle over (4)} is irradiated with light during the development of the resist, and the stopping time of the development for finishing the device pattern in a desired size is estimated on the basis of the change in the intensity of the reflected light of the monitor region. Further, a developing solution is supplied onto the wafer during the estimated stopping time of the development so as to stop the development.
    Type: Application
    Filed: June 29, 2001
    Publication date: February 7, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kei Hayasaki, Shinichi Ito
  • Patent number: 6251544
    Abstract: In an exposure dose measuring method for measuring an effective exposure dose on a wafer by printing mask patterns formed on a mask onto a resist coated on the wafer by exposure, each of the mask patterns has light transmitting sections and light shielding sections repeated in a period p, a ratio of areas of the light transmitting sections to areas of the light shielding sections of each of the mask patterns differs from ratios of those of the others of the mask patterns, and the period p is set so as to satisfy a relationship of p/M≦&lgr;/(1+&sgr;)NA, where an exposure light wavelength at the time of exposing the mask patterns is &lgr;, a numerical aperture at a wafer side is NA, an illumination coherence factor is &sgr;, and a mask pattern magnification for patterns to be formed on the wafer is M.
    Type: Grant
    Filed: June 17, 1999
    Date of Patent: June 26, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Inoue, Shinichi Ito, Kei Hayasaki
  • Publication number: 20010001463
    Abstract: A heating apparatus for performing heat treatment on a wafer applied with a resist before or after exposure includes a heating plate for heating a wafer which is placed on the heating plate, a light intensity detecting apparatus for irradiating light on the wafer to detect intensity of reflected light from the resist on the wafer, and a control section for controlling heating performed by the heating plate on the basis of the detected intensity of reflected light so that heating amount applied to a plurality of wafers becomes constant. Accordingly, the heating amount of the wafer can be controlled to be constant and variations in dimension of resist patterns can be reduced.
    Type: Application
    Filed: December 13, 2000
    Publication date: May 24, 2001
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kei Hayasaki, Shinichi Ito, Kenji Kawano
  • Patent number: 6191397
    Abstract: A heating apparatus for performing heat treatment on a wafer applied with a resist before or after exposure includes a heating plate for heating a wafer which is placed on the heating plate, a light intensity detecting apparatus for irradiating light on the wafer to detect intensity of reflected light from the resist on the wafer, and a control section for controlling heating performed by the heating plate on the basis of the detected intensity of reflected light so that heating amount applied to a plurality of wafers becomes constant. Accordingly, the heating amount of the wafer can be controlled to be constant and variations in dimension of resist patterns can be reduced.
    Type: Grant
    Filed: July 1, 1999
    Date of Patent: February 20, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Hayasaki, Shinichi Ito, Kenji Kawano
  • Patent number: 6187488
    Abstract: A pattern estimating method, wherein during exposure for forming the device pattern, a latent image of a monitor pattern which has the same pitch as an L/S pattern as the device pattern and has a narrower line width than the L/S pattern is formed in a mark area, after developing the device pattern, probing light is applied from a monitor head to the monitor pattern, and under the conditions for preventing generation of diffracted light of first-order or more, the intensity of zero-order light reflected from the monitor pattern is detected, so that the size of the device pattern is estimated on the basis of the prestored relationship between the device pattern size and the zero-order diffracted light intensity.
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: February 13, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Hayasaki, Shinichi Ito, Fumio Komatsu