Patents by Inventor Kei Kawahara
Kei Kawahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11980302Abstract: An air blower includes: a panel (3); a frame member (5) arranged to surround the panel (3) and having a blowout port (13a, 13b, 13c, 13d, 13e, 13f, 13g) of air formed therein; and a fan (11a, 11b, 11c, 11d, 11e, 11f, 30) that sends air to the blowout port (13a, 13b, 13c, 13d, 13e, 13f, 13g). The frame member (5) produces airflows that are blown out from at least three directions and collide with each other, thereby producing an air current going forward to the panel (3).Type: GrantFiled: November 30, 2020Date of Patent: May 14, 2024Assignee: DAIKIN INDUSTRIES, LTD.Inventors: Kei Takenaka, Yousuke Imai, Yuusuke Taruki, Keita Kawahara, Aya Okuno, Masahiko Chouji
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Publication number: 20220278368Abstract: Provided are a nonaqueous electrolyte solution which makes it possible to further improve low temperature characteristics and high temperature storage characteristics; and a nonaqueous electrolyte secondary battery comprising such a nonaqueous electrolyte solution. The present nonaqueous electrolyte solution comprises: (I) a first additive represented by the following formula [1], (II) at least one second additive selected from the group consisting of the compounds represented by the following formulae [2] to [5], difluoro(oxalato)borate, bis(oxalato)borate, tetrafluoro(oxalato)phosphate, difluorobis(oxalato)phosphate, tris(oxalato)phosphate, difluorophosphate, and fluorosulfonate, (III) a nonaqueous organic solvent, and (IV) a solute.Type: ApplicationFiled: July 6, 2020Publication date: September 1, 2022Applicant: CENTRAL GLASS CO., LTD.Inventors: Takayoshi MORINAKA, Wataru KAWABATA, Kei KAWAHARA, Mikihiro TAKAHASHI
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Publication number: 20210313624Abstract: The present invention provides: a nonaqueous electrolyte solution which is capable of improving the storage characteristics at high temperatures and the internal resistance characteristics after storage in a more balanced manner; and a nonaqueous electrolyte secondary battery which is provided with this nonaqueous electrolyte solution. A nonaqueous electrolyte solution according to the present invention contains (I) an imide anion of general formula [1] or [2], (II) a sulfonic acid salt of general formula [3], (III) a nonaqueous organic solvent or an ionic liquid; and (IV) a solute.Type: ApplicationFiled: August 16, 2019Publication date: October 7, 2021Applicant: CENTRAL GLASS CO., LTD.Inventors: Takayoshi MORINAKA, Kei KAWAHARA, Wataru KAWABATA, Katsumasa MORI, Mikihiro TAKAHASHI
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Patent number: 10930635Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.Type: GrantFiled: April 27, 2020Date of Patent: February 23, 2021Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
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Publication number: 20200258877Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.Type: ApplicationFiled: April 27, 2020Publication date: August 13, 2020Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
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Patent number: 10679979Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.Type: GrantFiled: October 3, 2018Date of Patent: June 9, 2020Assignee: Seiko Epson CorporationInventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
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Publication number: 20190035776Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.Type: ApplicationFiled: October 3, 2018Publication date: January 31, 2019Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
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Patent number: 10121741Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.Type: GrantFiled: February 24, 2017Date of Patent: November 6, 2018Assignee: Seiko Epson CorporationInventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
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Patent number: 9978737Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.Type: GrantFiled: August 22, 2016Date of Patent: May 22, 2018Assignee: Seiko Epson CorporationInventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
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Patent number: 9953922Abstract: A multilayer semiconductor device includes first wirings extending in a first direction adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and a second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The dummy wirings have a first dummy wiring, a second dummy wiring, a third dummy wiring, a fourth dummy wiring, and a fifth dummy wiring. When the dummy wirings are rotated around a center of the first dummy wiring through 90 degrees, centers of the second, third, fourth, and fifth dummy wirings are aligned with centers of the fourth, fifth, third, and second dummy wirings prior to being rotated.Type: GrantFiled: February 24, 2017Date of Patent: April 24, 2018Assignee: Seiko Epson CorporationInventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
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Publication number: 20170162498Abstract: A multilayer semiconductor device includes first wirings extending in a first direction adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and a second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The dummy wirings have a first dummy wiring, a second dummy wiring, a third dummy wiring, a fourth dummy wiring, and a fifth dummy wiring. When the dummy wirings are rotated around a center of the first dummy wiring through 90 degrees, centers of the second, third, fourth, and fifth dummy wirings are aligned with centers of the fourth, fifth, third, and second dummy wirings prior to being rotated.Type: ApplicationFiled: February 24, 2017Publication date: June 8, 2017Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
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Publication number: 20170162499Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.Type: ApplicationFiled: February 24, 2017Publication date: June 8, 2017Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
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Publication number: 20160358901Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.Type: ApplicationFiled: August 22, 2016Publication date: December 8, 2016Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
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Patent number: 9455223Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.Type: GrantFiled: February 4, 2015Date of Patent: September 27, 2016Assignee: Seiko Epson CorporationInventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
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Publication number: 20150155232Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.Type: ApplicationFiled: February 4, 2015Publication date: June 4, 2015Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
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Patent number: 8984466Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.Type: GrantFiled: December 20, 2013Date of Patent: March 17, 2015Assignee: Seiko Epson CorporationInventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
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Publication number: 20140110853Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.Type: ApplicationFiled: December 20, 2013Publication date: April 24, 2014Applicant: Seiko Epson CorporationInventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
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Patent number: 8637950Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.Type: GrantFiled: March 12, 2013Date of Patent: January 28, 2014Assignee: Seiko Epson CorporationInventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
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Patent number: 8418114Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.Type: GrantFiled: May 31, 2012Date of Patent: April 9, 2013Assignee: Seiko Epson CorporationInventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
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Publication number: 20120246603Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.Type: ApplicationFiled: May 31, 2012Publication date: September 27, 2012Applicant: SEIKO EPSON CORPORATIONInventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA