Abstract: An information processing apparatus includes a higher node having a plurality of weak discriminators that have learned a learning sample of a first label and a learning sample of a second label that has a predetermined coordinate relationship with the learning sample of the first label, a first lower node having a plurality of weak discriminators that have learned the learning sample of the first label based on the discrimination result of the higher node and a second lower node that has no weak discriminator.

Abstract: An information processing apparatus includes a higher node having a plurality of weak discriminators that have learned a learning sample of a first label and a learning sample of a second label that has a predetermined coordinate relationship with the learning sample of the first label, a first lower node having a plurality of weak discriminators that have learned the learning sample of the first label based on the discrimination result of the higher node and a second lower node that has no weak discriminator.

Abstract: A data processor includes a bus interface coupled to an external bus for transferring information to and from the external bus, an instruction decoding section coupled to the bus interface to receive an instruction through the bus interface from the external bus to decode the received instruction, and an instruction execution unit coupled to receive decoded information from the instruction decoding section to execute the received decoded information. The instruction decoding section includes an instruction decoder receiving an instruction through the bus interface to output the decoded information to the instruction execution unit and to generate tag information, an effective address generator receiving the tag information to calculate an effective address, and a memory management unit receiving the effective address to generate a real address.

Abstract: An arithmetic logic system includes a plurality of arithmetic logic units for processing data composed of a corresponding number of bits and having a path for transferring a carry through the respective arithmetic logic units, and a carry look-ahead circuit provided in parallel to the carry transfer path and having inputs respectively connected to the arithmetic logic units for generating a carry look-ahead signal when a carrry look-ahead condition is realized. A carry signal output is connected to a most upstream end of the carry transfer path, and a first transfer gate is connected at its one end to the carry signal output and at its other end to a predetermined voltage. The first transfer gate operates in response to the carry look-ahead signal so as to connect the carry signal output to the predetermined voltage. A second transfer gate is connected between the carry signal output and the most upstream end of the carry transfer path.

Abstract: A signal detecting circuit for detecting signals from a signal output circuit having a predetermined number of output terminals of which only one output terminal is to be normally selected during each recurrent cycle of operation, comprising the combination of a first circuit unit which has input terminals respectively connected to the output terminals of the signal output circuit and which has a first operative condition established with only one of the input terminals activated and a second operative condition established with at least two of the input terminals activated, the first circuit unit being operative to produce an output signal which has one voltage level under the first operative condition and another voltage level under the second operative condition, and a second circuit unit which is connected to the first circuit unit and which is operative to discriminate one of the first and second operative conditions from the other on the basis of the output signal from the first circuit unit.