Abstract: A normal array for storing data in a non-volatile manner is divided into m sectors each corresponding to a unit subjected to a single data write or erase operation (where m is a natural number). An extra memory array includes a plurality of extra sectors each corresponding to a unit subjected to a single data read operation. The number of extra sectors is equal to or smaller than m. Each extra sector stores the data of the data write conditions or erase conditions corresponding to one of the m sectors in a non-volatile manner. The data write operation or erase operation is conducted based on the information corresponding to a selected sector, which is read from the extra memory array.

Abstract: A normal array for storing data in a non-volatile manner is divided into m sectors each corresponding to a unit subjected to a single data write or erase operation (where m is a natural number). An extra memory array includes a plurality of extra sectors each corresponding to a unit subjected to a single data read operation. The number of extra sectors is equal to or smaller than m. Each extra sector stores the data of the data write conditions or erase conditions corresponding to one of the m sectors in a non-volatile manner. The data write operation or erase operation is conducted based on the information corresponding to a selected sector, which is read from the extra memory array.

Abstract: To provide a semiconductor memory capable of executing a read test at a high speed based on a comparatively complicated test pattern without increasing a circuit area. Every fifth node N1 of a latch L3 of a sense latch group 3 is connected to a gate of an NMOS transistor QLi (i=0 to 3) at 4 intervals and every fifth node N2 is connected to a gate of an NMOS transistor QRi at 4 intervals. The NMOS transistor QLi has a drain connected to a decision result line CHKiL and a source grounded. The NMOS transistor QRi has a drain connected to a decision result line CHKiR and a source grounded. An ALL deciding circuit 5A outputs, as a decision result ALL5, decision result signals ALL0L to ALL3L obtained from decision result lines CHK0L to CHK3L and decision result signals ALL0R to ALL3R obtained from decision result lines CHK0R to CHK3R.

Abstract: A nonvolatile semiconductor memory comprising an erase pulse generator, an erase pulse counter and an erase verify signal generator. The erase pulse counter counts erase pulses output by the erase pulse generator, and the erase verify signal generator generates an erase verify signal. The erase pulse counter keeps the erase verify signal generator inactive until the number of the counted erase pulses exceeds a predetermined count. Only erase operations are allowed to continue while erase verify operations are being suppressed, until the erase pulse count exceeds the predetermined count. The scheme shortens the erase time involved.