Patents by Inventor Kei-Yu Ko
Kei-Yu Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10811233Abstract: Process chambers having a tunable showerhead and a tunable liner are disclosed herein. In some embodiments, a processing chamber includes a showerhead; a chamber liner; a first impedance circuit coupled to the showerhead to tune an impedance of the showerhead; a second impedance circuit coupled to the chamber liner to tune an impedance of the chamber liner; and a controller coupled to the first and second impedance circuits to control relative impedances of the showerhead and the chamber liner.Type: GrantFiled: August 9, 2017Date of Patent: October 20, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Andrew Nguyen, Xue Yang Chang, Haitao Wang, Kei-Yu Ko, Reza Sadjadi
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Publication number: 20180047544Abstract: Process chambers having a tunable showerhead and a tunable liner are disclosed herein. In some embodiments, a processing chamber includes a showerhead; a chamber liner; a first impedance circuit coupled to the showerhead to tune an impedance of the showerhead; a second impedance circuit coupled to the chamber liner to tune an impedance of the chamber liner; and a controller coupled to the first and second impedance circuits to control relative impedances of the showerhead and the chamber liner.Type: ApplicationFiled: August 9, 2017Publication date: February 15, 2018Inventors: ANDREW NGUYEN, XUE YANG CHANG, HAITAO WANG, KEI-YU KO, REZA SADJADI
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Patent number: 7470628Abstract: Processes, etchants, and apparatus useful for etching an insulating oxide layer of a substrate without damaging underlying nitride features or field oxide regions. The processes exhibit good selectivity to both nitrides and field oxides. Integrated circuits produced utilizing etching processes of the present invention are much less likely to be defective due to photoresist mask misalignment. Etchants used in processes of the present invention comprise a carrier gas, one or more C2+F gases, CH2F2, and a gas selected from the group consisting of CHF3, CF4, and mixtures thereof. The processes can be performed at power levels lower than what is currently utilized in the prior art.Type: GrantFiled: May 17, 2005Date of Patent: December 30, 2008Assignee: Micron Technology, Inc.Inventor: Kei-Yu Ko
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Patent number: 7319075Abstract: A selective dry etch process includes use of an etchant that includes C2HxFy, where x is an integer from three to five, inclusive, where y is an integer from one to three, inclusive, and where x plus y equals six. The etchant etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C2HxFy-containing etchant. C2HxFy may be employed as either a primary etchant or as an additive to another etchant or etchant mixture.Type: GrantFiled: March 25, 2003Date of Patent: January 15, 2008Assignee: Micron Technology, Inc.Inventors: Kei-Yu Ko, Li Li, Guy T. Blalock
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Patent number: 7273566Abstract: Processes, etchants, and apparatus useful for etching an insulating oxide layer of a substrate without damaging underlying nitride features or field oxide regions. The processes exhibit good selectivity to both nitrides and field oxides. Integrated circuits produced utilizing etching processes of the present invention are much less likely to be defective due to photoresist mask misalignment. Etchants used in processes of the present invention comprise a carrier gas, one or more C2+F gases, CH2F2, and a gas selected from the group consisting of CHF3, CF4, and mixtures thereof. The processes can be performed at power levels lower than what is currently utilized in the prior art.Type: GrantFiled: July 7, 2005Date of Patent: September 25, 2007Assignee: Micron Technology, Inc.Inventor: Kei-Yu Ko
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Patent number: 7173339Abstract: An etchant including C2HxFy, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six, etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C2HxFy-containing etchant. C2HxFy may be employed as either a primary etchant or as an additive to another etchant or etchant mixture. The invention also includes semiconductor devices that include structures that have been patterned with an etchant of the present invention or in accordance with the method of the present invention. Specifically, the present invention includes semiconductor devices including doped silicon oxide structures with substantially vertical sidewalls and adjacent undoped silicon oxide or silicon nitride structures exposed adjacent the sidewall.Type: GrantFiled: June 1, 2000Date of Patent: February 6, 2007Assignee: Micron Technology, Inc.Inventors: Kei-Yu Ko, Li Li, Guy T. Blalock
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Patent number: 7094700Abstract: In one implementation, a plasma etching method comprises forming a GexSey chalcogenide comprising layer over a substrate. A mask comprising an organic masking material is formed over the GexSey chalcogenide comprising layer. The mask comprises a sidewall. At least prior to plasma etching the GexSey comprising layer, the sidewall of the mask is exposed to a fluorine comprising material. After said exposing, the GexSey chalcogenide comprising layer is plasma etched using the mask and a hydrogen containing etching gas. The plasma etching forms a substantially vertical sidewall of the GexSey chalcogenide comprising layer which is aligned with a lateral outermost extent of the sidewall of the mask.Type: GrantFiled: September 2, 2004Date of Patent: August 22, 2006Assignee: Micron Technology, Inc.Inventors: Li Li, Terry L. Gilton, Kei-Yu Ko, John T. Moore, Karen Signorini
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Patent number: 6989108Abstract: Processes, etchants, and apparatus useful for etching an insulating oxide layer of a substrate without damaging underlying nitride features or field oxide regions. The processes exhibit good selectivity to both nitrides and field oxides. Integrated circuits produced utilizing etching processes of the present invention are much less likely to be defective due to photoresist mask misalignment. Etchants used in processes of the present invention comprise a carrier gas, one or more C2+F gases, CH2F2, and a gas selected from the group consisting of CHF3, CF4, and mixtures thereof. The processes can be performed at power levels lower than what is currently utilized in the prior art.Type: GrantFiled: August 30, 2001Date of Patent: January 24, 2006Assignee: Micron Technology, Inc.Inventor: Kei-Yu Ko
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Publication number: 20060011579Abstract: Processes, etchants, and apparatus useful for etching an insulating oxide layer of a substrate without damaging underlying nitride features or field oxide regions. The processes exhibit good selectivity to both nitrides and field oxides. Integrated circuits produced utilizing etching processes of the present invention are much less likely to be defective due to photoresist mask misalignment. Etchants used in processes of the present invention comprise a carrier gas, one or more C2+F gases, CH2F2, and a gas selected from the group consisting of CHF3, CF4, and mixtures thereof. The processes can be performed at power levels lower than what is currently utilized in the prior art.Type: ApplicationFiled: July 7, 2005Publication date: January 19, 2006Inventor: Kei-Yu Ko
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Patent number: 6967408Abstract: The present invention relates to gate stack structure that is fabricated by a process for selectively plasma etching a structure upon a semiconductor substrate to form a designated topographical structure thereon utilizing an undoped silicon dioxide layer as an etch stop. In one embodiment, a substantially undoped silicon dioxide layer is formed upon a layer of semiconductor material. A doped silicon dioxide layer is then formed upon said undoped silicon dioxide layer. The doped silicon dioxide layer is etched to create the topographical structure. The etch has a material removal rate that is at least 10 times higher for doped silicon dioxide than for undoped silicon dioxide or the semiconductor material. One application of the inventive process includes selectively plasma etching a multilayer structure to form a self-aligned contact between adjacent gate stacks and a novel gate structure resulting therefrom.Type: GrantFiled: May 25, 2000Date of Patent: November 22, 2005Assignee: Micron Technology, Inc.Inventor: Kei-Yu Ko
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Publication number: 20050218373Abstract: Processes, etchants, and apparatus useful for etching an insulating oxide layer of a substrate without damaging underlying nitride features or field oxide regions. The processes exhibit good selectivity to both nitrides and field oxides. Integrated circuits produced utilizing etching processes of the present invention are much less likely to be defective due to photoresist mask misalignment. Etchants used in processes of the present invention comprise a carrier gas, one or more C2+F gases, CH2F2, and a gas selected from the group consisting of CHF3, CF4, and mixtures thereof. The processes can be performed at power levels lower than what is currently utilized in the prior art.Type: ApplicationFiled: May 17, 2005Publication date: October 6, 2005Inventor: Kei-Yu Ko
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Publication number: 20050211672Abstract: Processes, etchants, and apparatus useful for etching an insulating oxide layer of a substrate without damaging underlying nitride features or field oxide regions. The processes exhibit good selectivity to both nitrides and field oxides. Integrated circuits produced utilizing etching processes of the present invention are much less likely to be defective due to photoresist mask misalignment. Etchants used in processes of the present invention comprise a carrier gas, one or more C2+F gases, CH2F2, and a gas selected from the group consisting of CHF3, CF4, and mixtures thereof. The processes can be performed at power levels lower than what is currently utilized in the prior art.Type: ApplicationFiled: May 17, 2005Publication date: September 29, 2005Inventor: Kei-Yu Ko
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Patent number: 6875371Abstract: An etchant including C2HxFy, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C2HxFy-containing etchant. C2HxFy may be employed as either a primary etchant or as an additive to another etchant or etchant mixture.Type: GrantFiled: November 13, 2000Date of Patent: April 5, 2005Assignee: Micron Technology, Inc.Inventors: Kei-Yu Ko, Li Li, Guy T. Blalock
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Publication number: 20050054207Abstract: In one implementation, a plasma etching method comprises forming a GexSey chalcogenide comprising layer over a substrate. A mask comprising an organic masking material is formed over the GexSey chalcogenide comprising layer. The mask comprises a sidewall. At least prior to plasma etching the GexSey comprising layer, the sidewall of the mask is exposed to a fluorine comprising material. After said exposing, the GexSey chalcogenide comprising layer is plasma etched using the mask and a hydrogen containing etching gas. The plasma etching forms a substantially vertical sidewall of the GexSey chalcogenide comprising layer which is aligned with a lateral outermost extent of the sidewall of the mask.Type: ApplicationFiled: September 2, 2004Publication date: March 10, 2005Applicant: MICRON TECHNOLOGY, INC.Inventors: Li Li, Terry Gilton, Kei-Yu Ko, John Moore, Karen Signorini
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Patent number: 6849557Abstract: The present invention relates to a process for selectively plasma etching a structure upon a semiconductor substrate to form designated topographical structure thereon utilizing an undoped silicon dioxide layer as an etch stop. In one embodiment, a substantially undoped silicon dioxide layer is formed upon a layer of semiconductor material. A doped silicon dioxide layer is then formed upon said undoped silicon dioxide layer. The doped silicon dioxide layer is etched to create the topographical structure. The etch has a material removal rate that is at least 10 times higher for doped silicon dioxide than for undoped silicon dioxide or the semiconductor material. One application of the inventive process includes selectively plasma etching a multilayer structure to form a self-aligned contact between adjacent gate stacks and a novel gate structure resulting therefrom. In the application, a multilayer structure is first formed comprising layers of silicon, gate oxide, polysilicon, and tungsten silicide.Type: GrantFiled: April 30, 1997Date of Patent: February 1, 2005Assignee: Micron Technology, Inc.Inventor: Kei-Yu Ko
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Patent number: 6831019Abstract: In one implementation, a plasma etching method comprises forming a GexSey chalcogenide comprising layer over a substrate. A mask comprising an organic masking material is formed over the GexSey chalcogenide comprising layer. The mask comprises a sidewall. At least prior to plasma etching the GexSey comprising layer, the sidewall of the mask is exposed to a fluorine comprising material. After exposing, the GexSey chalcogenide comprising layer is plasma etched using the mask and a hydrogen containing etching gas. The plasma etching forms a substantially vertical sidewall of the GexSey chalcogenide comprising layer which is aligned with a lateral outermost extent of the sidewall of the mask.Type: GrantFiled: August 29, 2002Date of Patent: December 14, 2004Assignee: Micron Technology, Inc.Inventors: Li Li, Terry L. Gilton, Kei-Yu Ko, John T. Moore, Karen Signorini
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Patent number: 6716766Abstract: A method for forming an opening through an interlayer to expose an underlying surface that retains high etch selectivity while having a relatively large process window to accommodate process variations. The method etches an interlayer under a first etching condition that forms a protective layer over portions of exposed surfaces of the opening during the etch process. The formation of the protective layer continues until an etch stop condition is produced, stopping further etching of the interlayer under the first condition prior to exposing the underlying surface. The method continues with etching through the protective layer under a second etching condition to expose a residual interlayer, and etching the exposed residual interlayer under the second etching condition to expose the underlying surface.Type: GrantFiled: August 22, 2002Date of Patent: April 6, 2004Assignee: Micron Technology, Inc.Inventor: Kei-Yu Ko
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Publication number: 20040038546Abstract: A method for forming an opening through an interlayer to expose an underlying surface that retains high etch selectivity while having a relatively large process window to accommodate process variations. The method etches an interlayer under a first etching condition that forms a protective layer over portions of exposed surfaces of the opening during the etch process. The formation of the protective layer continues until an etch stop condition is produced, stopping further etching of the interlayer under the first condition prior to exposing the underlying surface. The method continues with etching through the protective layer under a second etching condition to expose a residual interlayer, and etching the exposed residual interlayer under the second etching condition to expose the underlying surface.Type: ApplicationFiled: August 22, 2002Publication date: February 26, 2004Inventor: Kei-Yu Ko
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Publication number: 20030203639Abstract: A selective dry etch process includes use of an etchant that includes C2HxFy, where x is an integer from three to five, inclusive, where y is an integer from one to three, inclusive, and where x plus y equals six. The etchant etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C2HxFy-containing etchant. C2HxFy may be employed as either a primary etchant or as an additive to another etchant or etchant mixture.Type: ApplicationFiled: March 25, 2003Publication date: October 30, 2003Inventors: Kei-Yu Ko, Li Li, Guy T. Blalock
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Patent number: 6551940Abstract: Disclosed is a process of using undoped silicon dioxide as an etch mask for selectively etching doped silicon dioxide for forming a designated topographical structure. In one embodiment, a doped silicon dioxide layer is formed over a semiconductor substrate. An undoped silicon dioxide layer is formed and patterned over the doped silicon dioxide layer. Doped silicon dioxide is selectively removed from the doped silicon dioxide layer through the pattern by use of a plasma etch or another suitable etch that removes doped silicon dioxide at a rate greater than that of undoped silicon dioxide. The process may be used to form contacts to the semiconductor substrate. The process may also be used to form a structure with a lower and an upper series of parallel gate stacks, where the gate stacks have upper surfaces consisting essentially of undoped silicon dioxide.Type: GrantFiled: October 27, 1997Date of Patent: April 22, 2003Assignee: Micron Technology, Inc.Inventor: Kei-Yu Ko